On Fri, Apr 23, 2021 at 03:47:29AM +0200, Ansuel Smith wrote:
> With the use of the qca8k dsa driver, some problem arised related to
> port status detection. With a load on a specific port (for example a
> simple speed test), the driver starts to bheave in a strange way and
> garbage data is produced. To address this, enlarge the sleep delay and
> address a bug for the reg offset 31 that require additional delay for
> this specific reg.
> struct ipq8064_mdio {
> struct regmap *base; /* NSS_GMAC0_BASE */
> @@ -65,7 +66,7 @@ ipq8064_mdio_read(struct mii_bus *bus, int phy_addr, int reg_offset)
> ((reg_offset << MII_REG_SHIFT) & MII_REG_MASK);
>
> regmap_write(priv->base, MII_ADDR_REG_ADDR, miiaddr);
> - usleep_range(8, 10);
> + usleep_range(10, 13);
>
> err = ipq8064_mdio_wait_busy(priv);
> if (err)
> @@ -91,7 +92,14 @@ ipq8064_mdio_write(struct mii_bus *bus, int phy_addr, int reg_offset, u16 data)
> ((reg_offset << MII_REG_SHIFT) & MII_REG_MASK);
>
> regmap_write(priv->base, MII_ADDR_REG_ADDR, miiaddr);
> - usleep_range(8, 10);
> +
> + /* For the specific reg 31 extra time is needed or the next
> + * read will produce grabage data.
> + */
> + if (reg_offset == 31)
> + usleep_range(30, 43);
> + else
> + usleep_range(10, 13);
>
> return ipq8064_mdio_wait_busy(priv);
Is there any documentation as to what register 31 does?
Maybe the real problem is in ipq8064_mdio_wait_busy()? Have you looked
at how long you typically end up waiting? If you know the MDIO bus
speed, you can work out how long a transaction should take. If it is
taking less, something is broken.
Are you sure regmap caching is disabled, so that
ipq8064_mdio_wait_busy() really is reading the register, not some
old cached value?
Andrew
> }
> --
> 2.30.2
>
