Quoting Michal Simek (2021-04-08 03:40:29) > > > On 4/8/21 12:26 PM, Shubhrajyoti Datta wrote: > > On Sun, Mar 7, 2021 at 1:50 AM Rob Herring <robh@xxxxxxxxxx> wrote: > >> > >> On Wed, Feb 24, 2021 at 06:40:40PM +0530, Shubhrajyoti Datta wrote: > >>> Add the devicetree binding for the xilinx clocking wizard. > >>> > >>> Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xxxxxxxxxx> > >>> --- > >>> v6: > >>> Fix a yaml warning > >>> v7: > >>> Add vendor prefix speed-grade > >>> v8: > >>> Fix the warnings > >>> v10: > >>> Add nr-outputs > >>> > >>> .../bindings/clock/xlnx,clocking-wizard.yaml | 72 ++++++++++++++++++++++ > >>> 1 file changed, 72 insertions(+) > >>> create mode 100644 Documentation/devicetree/bindings/clock/xlnx,clocking-wizard.yaml > >>> > >>> diff --git a/Documentation/devicetree/bindings/clock/xlnx,clocking-wizard.yaml b/Documentation/devicetree/bindings/clock/xlnx,clocking-wizard.yaml > >>> new file mode 100644 > >>> index 0000000..280eb09 > >>> --- /dev/null > >>> +++ b/Documentation/devicetree/bindings/clock/xlnx,clocking-wizard.yaml > >>> @@ -0,0 +1,72 @@ > >>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > >>> +%YAML 1.2 > >>> +--- > >>> +$id: "http://devicetree.org/schemas/clock/xlnx,clocking-wizard.yaml#"; > >>> +$schema: "http://devicetree.org/meta-schemas/core.yaml#"; > >>> + > >>> +title: Xilinx clocking wizard > >>> + > >>> +maintainers: > >>> + - Shubhrajyoti Datta <shubhrajyoti.datta@xxxxxxxxxx> > >>> + > >>> +description: > >>> + The clocking wizard is a soft ip clocking block of Xilinx versal. It > >>> + reads required input clock frequencies from the devicetree and acts as clock > >>> + clock output. > >>> + > >>> +properties: > >>> + compatible: > >>> + const: xlnx,clocking-wizard > >> > >> Not very specific. Only 1 version of this h/w? > > > > Will fix in next version > >> > >>> + > >>> + reg: > >>> + maxItems: 1 > >>> + > >>> + "#clock-cells": > >>> + const: 1 > >>> + > >>> + clocks: > >>> + items: > >>> + - description: clock input > >>> + - description: axi clock > >>> + > >>> + clock-names: > >>> + items: > >>> + - const: clk_in1 > >>> + - const: s_axi_aclk > >>> + > >>> + > >>> + xlnx,speed-grade: > >>> + $ref: /schemas/types.yaml#/definitions/uint32 > >>> + enum: [1, 2, 3] > >>> + description: > >>> + Speed grade of the device. Higher the speed grade faster is the FPGA device. > >> > >> How does one decide what value? > > This is a property of the FPGA fabric. > > So hdf/xsa should tell that > > Shubhrajyoti: Rob likely doesn't know what hdf/xsa is that's why it is > better to avoid it. > > fpgas/pl part of SoC are tested for performance and different chips have > different speed grades. This is done for every chip and some chips are > faster/slower. Based on this speed grade is labeled. And there is no way > how to find at run time which speed grade your device has. That's why > there is a need to have property to identify this. > > In designed tools it is your responsibility to select proper chip based > on your order and then this value is propagated in Xilinx standard way > via device tree generator to fill the right value for this property. The OPP framework and binding has support for speed grades via the 'supported-hw' property. I expect this speed-grade property could be dropped and an opp table could be assigned to the clk controller node for this speed grade by the DT author. Unfortunate that it isn't burned somewhere into the device so that software can pick the right frequency limits that way.
