On Tue, Apr 06, 2021 at 05:50:52PM +0200, Johan Jonker wrote:
> Current dts files with 'pwm' nodes are manually verified.
> In order to automate this process pwm-rockchip.txt
> has to be converted to yaml.
>
> Signed-off-by: Johan Jonker <jbx6244@xxxxxxxxx>
> ---
> .../devicetree/bindings/pwm/pwm-rockchip.txt | 27 ---------
> .../devicetree/bindings/pwm/pwm-rockchip.yaml | 66 ++++++++++++++++++++++
> 2 files changed, 66 insertions(+), 27 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/pwm/pwm-rockchip.txt
> create mode 100644 Documentation/devicetree/bindings/pwm/pwm-rockchip.yaml
>
> diff --git a/Documentation/devicetree/bindings/pwm/pwm-rockchip.txt b/Documentation/devicetree/bindings/pwm/pwm-rockchip.txt
> deleted file mode 100644
> index f70956dea..000000000
> --- a/Documentation/devicetree/bindings/pwm/pwm-rockchip.txt
> +++ /dev/null
> @@ -1,27 +0,0 @@
> -Rockchip PWM controller
> -
> -Required properties:
> - - compatible: should be "rockchip,<name>-pwm"
> - "rockchip,rk2928-pwm": found on RK29XX,RK3066 and RK3188 SoCs
> - "rockchip,rk3288-pwm": found on RK3288 SOC
> - "rockchip,rv1108-pwm", "rockchip,rk3288-pwm": found on RV1108 SoC
> - "rockchip,vop-pwm": found integrated in VOP on RK3288 SoC
> - - reg: physical base address and length of the controller's registers
> - - clocks: See ../clock/clock-bindings.txt
> - - For older hardware (rk2928, rk3066, rk3188, rk3228, rk3288, rk3399):
> - - There is one clock that's used both to derive the functional clock
> - for the device and as the bus clock.
> - - For newer hardware (rk3328 and future socs): specified by name
> - - "pwm": This is used to derive the functional clock.
> - - "pclk": This is the APB bus clock.
> - - #pwm-cells: must be 2 (rk2928) or 3 (rk3288). See pwm.yaml in this directory
> - for a description of the cell format.
> -
> -Example:
> -
> - pwm0: pwm@20030000 {
> - compatible = "rockchip,rk2928-pwm";
> - reg = <0x20030000 0x10>;
> - clocks = <&cru PCLK_PWM01>;
> - #pwm-cells = <2>;
> - };
> diff --git a/Documentation/devicetree/bindings/pwm/pwm-rockchip.yaml b/Documentation/devicetree/bindings/pwm/pwm-rockchip.yaml
> new file mode 100644
> index 000000000..cfd637d3e
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pwm/pwm-rockchip.yaml
> @@ -0,0 +1,66 @@
> +# SPDX-License-Identifier: GPL-2.0
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/pwm/pwm-rockchip.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Rockchip PWM controller
> +
> +maintainers:
> + - Heiko Stuebner <heiko@xxxxxxxxx>
> +
> +properties:
> + compatible:
> + oneOf:
> + - const: rockchip,rk2928-pwm
> + - const: rockchip,rk3288-pwm
> + - const: rockchip,vop-pwm
> + - items:
> + - enum:
> + - rockchip,rv1108-pwm
> + - const: rockchip,rk3288-pwm
> +
> + reg:
> + maxItems: 1
> +
> + clocks:
> + minItems: 1
> + maxItems: 2
> + description:
> + For older hardware (rk2928, rk3066, rk3188, rk3228, rk3288, rk3399)
> + There is one clock that is used both to derive the functional clock
> + for the device and as the bus clock.
> + For newer hardware (rk3328 and future SoCs) that is also specified
Can you express this with a schema.
> + with clock names.
> + "pwm" is used to derive the functional clock for the device.
> + "pclk" is used as the APB bus clock.
Let's not document the names twice.
> +
> + clock-names:
> + minItems: 1
> + items:
> + - const: pwm
> + - const: pclk
> +
> + "#pwm-cells":
> + enum: [2, 3]
> + description:
> + Must be 2 (rk2928) or 3 (rk3288).
> + See pwm.yaml for a description of the cell format.
> +
> +additionalProperties: false
> +
> +required:
> + - compatible
> + - reg
> + - clocks
> + - "#pwm-cells"
> +
> +examples:
> + - |
> + #include <dt-bindings/clock/rk3188-cru-common.h>
> + pwm0: pwm@20030000 {
> + compatible = "rockchip,rk2928-pwm";
> + reg = <0x20030000 0x10>;
> + clocks = <&cru PCLK_PWM01>;
> + #pwm-cells = <2>;
> + };
> --
> 2.11.0
>
