On Wed, 2021-04-07 at 13:17 +0200, Matthias Brugger wrote: > > From the binding description: > - #address-cells: should be 1. > > - #size-cells: should be 0. > > We are missing both here. Please fix that. > > Apart the binding description is naming PLL, clock mux and clock gate IDs which > do not correspond to the ones used here. It seems that this binding was tailored > for a specific SoC family but never made generic. If you want, please do so and > convert it to yaml. Dear Matthias: I have update patch v2: https://patchwork.kernel.org/project/linux-mediatek/patch/20210409015651.11474-1-Mason.Zhang@xxxxxxxxxxxx/ Please gentle ping on this patch. Thanks~ Thanks Mason
