On Thu, Apr 01, 2021 at 02:38:02PM +0800, Nina Wu wrote:
> From: Nina Wu <Nina-CM.Wu@xxxxxxxxxxxx>
Every change is an 'update'. Perhaps mention mt8192 in the subject.
>
> To support newer hardware architecture of devapc,
> update device tree bindings.
>
> Signed-off-by: Nina Wu <Nina-CM.Wu@xxxxxxxxxxxx>
> ---
> Documentation/devicetree/bindings/soc/mediatek/devapc.yaml | 8 ++++++++
> 1 file changed, 8 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/soc/mediatek/devapc.yaml b/Documentation/devicetree/bindings/soc/mediatek/devapc.yaml
> index 31e4d3c..42b284e 100644
> --- a/Documentation/devicetree/bindings/soc/mediatek/devapc.yaml
> +++ b/Documentation/devicetree/bindings/soc/mediatek/devapc.yaml
> @@ -20,11 +20,17 @@ properties:
> compatible:
> enum:
> - mediatek,mt6779-devapc
> + - mediatek,mt8192-devapc
>
> reg:
> description: The base address of devapc register bank
> maxItems: 1
>
> + vio-idx-num:
Needs a vendor prefix.
> + description: The number of the devices controlled by devapc
> + $ref: /schemas/types.yaml#/definitions/uint32
> + maxItems: 1
> +
> interrupts:
> description: A single interrupt specifier
> maxItems: 1
> @@ -40,6 +46,7 @@ properties:
> required:
> - compatible
> - reg
> + - vio-idx-num
> - interrupts
> - clocks
> - clock-names
> @@ -54,6 +61,7 @@ examples:
> devapc: devapc@10207000 {
> compatible = "mediatek,mt6779-devapc";
> reg = <0x10207000 0x1000>;
> + vio-idx-num = <511>;
> interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_LOW>;
> clocks = <&infracfg_ao CLK_INFRA_DEVICE_APC>;
> clock-names = "devapc-infra-clock";
> --
> 2.6.4
>
