On 11/07/14 17:57, Thierry Reding wrote:
I don't think that's going to work? The voltage scaling is handled in hw.
Do we have to handle it in hardware or can we opt to do it in software,
too?
With the PLLX, voltage scaling is done entirely in SW. With the DFLL,
it's possible to stay in open-loop mode and do it in SW, but there's
not much point in that.
--
nvpublic
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo@xxxxxxxxxxxxxxx
More majordomo info at http://vger.kernel.org/majordomo-info.html
