Documentation to the Xilinx PSGTR Phy device-tree not clear

[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

 



Hi,

we try to port the mainline Kernel to a Xilinx board.

The default peripherals do work. The blocking point now is the zynqmp psgtr driver.

The mainline documentation can be found here:

https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/devicetree/bindings/phy/xlnx,zynqmp-psgtr.yaml

It is lacking a complete example on how to wire up a peripheral phy with the PS GTR driver.


The one in the Xilinx tree for Kernel 5.4 contains an example which is missing in the mainline documentation in my opinion:

https://github.com/Xilinx/linux-xlnx/blob/4ecd768dea75a0cc0bea91069a570981aa700744/Documentation/devicetree/bindings/phy/phy-zynqmp.txt


It seems the PHY handle mechanism has changed and the "old" Xilinx way doesn't work anymore.

This was the previous way to "marry" the PS GTR driver with the USB 3 driver:

       serdes: zynqmp_phy@fd400000 {
            compatible = "xlnx,zynqmp-psgtr-v1.1";
            status = "disabled";
            reg = <0x0 0xfd400000 0x0 0x40000>,
                  <0x0 0xfd3d0000 0x0 0x1000>;
            reg-names = "serdes", "siou";
            nvmem-cells = <&soc_revision>;
            nvmem-cell-names = "soc_revision";
            resets = <&zynqmp_reset ZYNQMP_RESET_SATA>, <&zynqmp_reset ZYNQMP_RESET_USB0_CORERESET>,                  <&zynqmp_reset ZYNQMP_RESET_USB1_CORERESET>, <&zynqmp_reset ZYNQMP_RESET_USB0_HIBERRESET>,                  <&zynqmp_reset ZYNQMP_RESET_USB1_HIBERRESET>, <&zynqmp_reset ZYNQMP_RESET_USB0_APB>,                  <&zynqmp_reset ZYNQMP_RESET_USB1_APB>, <&zynqmp_reset ZYNQMP_RESET_DP>,                  <&zynqmp_reset ZYNQMP_RESET_GEM0>, <&zynqmp_reset ZYNQMP_RESET_GEM1>,                  <&zynqmp_reset ZYNQMP_RESET_GEM2>, <&zynqmp_reset ZYNQMP_RESET_GEM3>;
            reset-names = "sata_rst", "usb0_crst", "usb1_crst",
                      "usb0_hibrst", "usb1_hibrst", "usb0_apbrst",
                      "usb1_apbrst", "dp_rst", "gem0_rst",
                      "gem1_rst", "gem2_rst", "gem3_rst";
            lane0: lane0 {
                #phy-cells = <4>;
            };
            lane1: lane1 {
                #phy-cells = <4>;
            };
            lane2: lane2 {
                #phy-cells = <4>;
            };
            lane3: lane3 {
                #phy-cells = <4>;
            };
        };


&dwc3_0 {
    status = "okay";
    dr_mode = "peripheral";
    phy-names = "usb3-phy";
    phys = <&lane2 4 0 0 26000000>;
    maximum-speed = "super-speed";
};


Regards,

Marco






[Index of Archives]     [Device Tree Compilter]     [Device Tree Spec]     [Linux Driver Backports]     [Video for Linux]     [Linux USB Devel]     [Linux PCI Devel]     [Linux Audio Users]     [Linux Kernel]     [Linux SCSI]     [XFree86]     [Yosemite Backpacking]


  Powered by Linux