On Fri 02 Apr 18:39 CDT 2021, Dmitry Baryshkov wrote:
> Specify input clocks to the SDM845's Global Clock Controller as required
> by the bindings.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@xxxxxxxxxx>
Okay, so that proved me wrong on my suggestion to rely on bi_tcxo always
coming from the DT...
Reviewed-by: Bjorn Andersson <bjorn.andersson@xxxxxxxxxx>
Regards,
Bjorn
> ---
> arch/arm64/boot/dts/qcom/sdm845.dtsi | 12 ++++++++++++
> 1 file changed, 12 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
> index 454f794af547..86f717d5bfb6 100644
> --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
> @@ -1061,6 +1061,16 @@ soc: soc@0 {
> gcc: clock-controller@100000 {
> compatible = "qcom,gcc-sdm845";
> reg = <0 0x00100000 0 0x1f0000>;
> + clocks = <&rpmhcc RPMH_CXO_CLK>,
> + <&rpmhcc RPMH_CXO_CLK_A>,
> + <&sleep_clk>,
> + <&pcie0_lane>,
> + <&pcie1_lane>;
> + clock-names = "bi_tcxo",
> + "bi_tcxo_ao",
> + "sleep_clk",
> + "pcie_0_pipe_clk",
> + "pcie_1_pipe_clk";
> #clock-cells = <1>;
> #reset-cells = <1>;
> #power-domain-cells = <1>;
> @@ -2062,6 +2072,7 @@ pcie0_lane: lanes@1c06200 {
> clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
> clock-names = "pipe0";
>
> + #clock-cells = <0>;
> #phy-cells = <0>;
> clock-output-names = "pcie_0_pipe_clk";
> };
> @@ -2170,6 +2181,7 @@ pcie1_lane: lanes@1c06200 {
> clocks = <&gcc GCC_PCIE_1_PIPE_CLK>;
> clock-names = "pipe0";
>
> + #clock-cells = <0>;
> #phy-cells = <0>;
> clock-output-names = "pcie_1_pipe_clk";
> };
> --
> 2.30.2
>
