On 2021/4/2 1:11, Will Deacon wrote: > On Thu, Apr 01, 2021 at 05:47:19PM +0200, Jean-Philippe Brucker wrote: >> The SMMU provides a Stall model for handling page faults in platform >> devices. It is similar to PCIe PRI, but doesn't require devices to have >> their own translation cache. Instead, faulting transactions are parked >> and the OS is given a chance to fix the page tables and retry the >> transaction. >> >> Enable stall for devices that support it (opt-in by firmware). When an >> event corresponds to a translation error, call the IOMMU fault handler. >> If the fault is recoverable, it will call us back to terminate or >> continue the stall. > > Which hardware is this useful for? Stalling adds a fair amount of complexity > to the driver, so I don't think we should support it unless we're likely to > see platforms that both implement it and do something useful with it. Hi Will， HiSilicon Kunpeng920's ZIP/SEC/HPRE engines(drivers/crypto/hisilicon/) are using stall mode. UACCE driver(drivers/misc/uacce/) is used to export these engines to user space. A user space library: https://github.com/Linaro/uadk offers APIs to help users to use these engines. In fact, we only need a quirk(https://lkml.org/lkml/2021/3/8/1506) based on this IOPF series to make whole solution mainline ready. So please also take this patch, we need it! :) Best, Zhou > > Will > > . >
