The clkgen-pll driver now embed the clock names (assuming the
right compatible is used). Remove all clock-output-names property
and update when necessary the compatible.
Signed-off-by: Alain Volmat <avolmat@xxxxxx>
---
arch/arm/boot/dts/stih418-clock.dtsi | 14 +++-----------
1 file changed, 3 insertions(+), 11 deletions(-)
diff --git a/arch/arm/boot/dts/stih418-clock.dtsi b/arch/arm/boot/dts/stih418-clock.dtsi
index 35d12979cdf4..d628e656458d 100644
--- a/arch/arm/boot/dts/stih418-clock.dtsi
+++ b/arch/arm/boot/dts/stih418-clock.dtsi
@@ -39,8 +39,6 @@
compatible = "st,stih418-clkgen-plla9";
clocks = <&clk_sysin>;
-
- clock-output-names = "clockgen-a9-pll-odf";
};
};
@@ -75,11 +73,9 @@
clk_s_a0_pll: clk-s-a0-pll {
#clock-cells = <1>;
- compatible = "st,clkgen-pll0";
+ compatible = "st,clkgen-pll0-a0";
clocks = <&clk_sysin>;
-
- clock-output-names = "clk-s-a0-pll-ofd-0";
};
clk_s_a0_flexgen: clk-s-a0-flexgen {
@@ -111,20 +107,16 @@
clk_s_c0_pll0: clk-s-c0-pll0 {
#clock-cells = <1>;
- compatible = "st,clkgen-pll0";
+ compatible = "st,clkgen-pll0-c0";
clocks = <&clk_sysin>;
-
- clock-output-names = "clk-s-c0-pll0-odf-0";
};
clk_s_c0_pll1: clk-s-c0-pll1 {
#clock-cells = <1>;
- compatible = "st,clkgen-pll1";
+ compatible = "st,clkgen-pll1-c0";
clocks = <&clk_sysin>;
-
- clock-output-names = "clk-s-c0-pll1-odf-0";
};
clk_s_c0_flexgen: clk-s-c0-flexgen {
--
2.17.1
