There is no binding and driver for the PMIC itself, but making the bus
available allows to access its registers using i2c-tools at least.
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@xxxxxxxxxxxxxx>
---
arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
index 7db4273cc88b..69e5c965930c 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
@@ -102,6 +102,15 @@ ethphy1: ethernet-phy@1 {
};
};
+&i2c1 {
+ clock-frequency = <400000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ status = "okay";
+
+ /* PMIC PCA9450C at address 0x25, irq to GPIO1_IO03. */
+};
+
&i2c3 {
clock-frequency = <400000>;
pinctrl-names = "default";
@@ -227,6 +236,13 @@ MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16 0x19
>;
};
+ pinctrl_i2c1: i2c1grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c3
+ MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c3
+ >;
+ };
+
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c3
--
2.29.2
