On Mon, Mar 15, 2021 at 9:26 AM Sander Vanheule <sander@xxxxxxxxxxxxx> wrote:
> Realtek MIPS SoCs (platform name Otto) have GPIO controllers with up to
> 64 GPIOs, divided over two banks. Each bank has a set of registers for
> 32 GPIOs, with support for edge-triggered interrupts.
>
> Each GPIO bank consists of four 8-bit GPIO ports (ABCD and EFGH). Most
> registers pack one bit per GPIO, except for the IMR register, which
> packs two bits per GPIO (AB-CD).
>
> Although the byte order is currently assumed to have port A..D at offset
> 0x0..0x3, this has been observed to be reversed on other, Lexra-based,
> SoCs (e.g. RTL8196E/97D/97F).
>
> Interrupt support is disabled for the fallback devicetree-compatible
> 'realtek,otto-gpio'. This allows for quick support of GPIO banks in
> which the byte order would be unknown. In this case, the port ordering
> in the IMR registers may not match the reversed order in the other
> registers (DCBA, and BA-DC or DC-BA).
>
> Signed-off-by: Sander Vanheule <sander@xxxxxxxxxxxxx>
Overall this is a beautiful driver and it makes use of all the generic
frameworks I can think of. I don't see any reason not to merge
it so:
Reviewed-by: Linus Walleij <linus.walleij@xxxxxxxxxx>
The following is some notes and nitpicks, nothing blocking any
merge, more like discussion.
> +enum realtek_gpio_flags {
> + GPIO_INTERRUPTS = BIT(0),
> +};
I suppose this looks like this because more flags will be introduced
when you add more functionality to the driver. Otherwise it seems
like overkill so a bool would suffice.
I would add a comment /* TODO: this will be expanded */
> +static inline u32 realtek_gpio_imr_bits(unsigned int pin, u32 value)
> +{
> + return ((value & 0x3) << 2*(pin % 16));
> +}
I would explain a bit about this, obviouslt it is two bit per
line, but it took me some time to parse, so a comment
about the bit layout would be nice.
> + unsigned int offset = pin/16;
Here that number appears again.
The use of GPIO_GENERIC and GPIO irqchip is flawless
and first class.
Thanks!
Linus Walleij
