NVIDIA Tegra SoCs have multiple power domains, each domain corresponds
to an external SoC power rail. Core power domain covers vast majority of
hardware blocks within a Tegra SoC. The voltage of a power domain should
be set to a value which satisfies all devices within a power domain. Add
driver for the core power domain which manages the voltage state of the
domain. This allows us to support a system-wide DVFS on Tegra.
Tested-by: Peter Geis <pgwipeout@xxxxxxxxx> # Ouya T30
Tested-by: Paul Fertser <fercerpav@xxxxxxxxx> # PAZ00 T20
Tested-by: Nicolas Chauvet <kwizart@xxxxxxxxx> # PAZ00 T20 and TK1 T124
Tested-by: Matt Merhar <mattmerhar@xxxxxxxxxxxxxx> # Ouya T30
Signed-off-by: Dmitry Osipenko <digetx@xxxxxxxxx>
---
drivers/soc/tegra/Kconfig | 6 +
drivers/soc/tegra/Makefile | 1 +
drivers/soc/tegra/core-power-domain.c | 153 ++++++++++++++++++++++++++
include/soc/tegra/common.h | 6 +
4 files changed, 166 insertions(+)
create mode 100644 drivers/soc/tegra/core-power-domain.c
diff --git a/drivers/soc/tegra/Kconfig b/drivers/soc/tegra/Kconfig
index bcd61ae59ba3..fccbc168dd87 100644
--- a/drivers/soc/tegra/Kconfig
+++ b/drivers/soc/tegra/Kconfig
@@ -16,6 +16,7 @@ config ARCH_TEGRA_2x_SOC
select SOC_TEGRA_COMMON
select SOC_TEGRA_FLOWCTRL
select SOC_TEGRA_PMC
+ select SOC_TEGRA_CORE_POWER_DOMAIN
select SOC_TEGRA20_VOLTAGE_COUPLER
select TEGRA_TIMER
help
@@ -31,6 +32,7 @@ config ARCH_TEGRA_3x_SOC
select SOC_TEGRA_COMMON
select SOC_TEGRA_FLOWCTRL
select SOC_TEGRA_PMC
+ select SOC_TEGRA_CORE_POWER_DOMAIN
select SOC_TEGRA30_VOLTAGE_COUPLER
select TEGRA_TIMER
help
@@ -170,3 +172,7 @@ config SOC_TEGRA20_VOLTAGE_COUPLER
config SOC_TEGRA30_VOLTAGE_COUPLER
bool "Voltage scaling support for Tegra30 SoCs"
depends on ARCH_TEGRA_3x_SOC || COMPILE_TEST
+
+config SOC_TEGRA_CORE_POWER_DOMAIN
+ bool
+ select PM_GENERIC_DOMAINS
diff --git a/drivers/soc/tegra/Makefile b/drivers/soc/tegra/Makefile
index 9c809c1814bd..8f1294f954b4 100644
--- a/drivers/soc/tegra/Makefile
+++ b/drivers/soc/tegra/Makefile
@@ -7,3 +7,4 @@ obj-$(CONFIG_SOC_TEGRA_PMC) += pmc.o
obj-$(CONFIG_SOC_TEGRA_POWERGATE_BPMP) += powergate-bpmp.o
obj-$(CONFIG_SOC_TEGRA20_VOLTAGE_COUPLER) += regulators-tegra20.o
obj-$(CONFIG_SOC_TEGRA30_VOLTAGE_COUPLER) += regulators-tegra30.o
+obj-$(CONFIG_SOC_TEGRA_CORE_POWER_DOMAIN) += core-power-domain.o
diff --git a/drivers/soc/tegra/core-power-domain.c b/drivers/soc/tegra/core-power-domain.c
new file mode 100644
index 000000000000..c118933d4252
--- /dev/null
+++ b/drivers/soc/tegra/core-power-domain.c
@@ -0,0 +1,153 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * NVIDIA Tegra SoC Core Power Domain Driver
+ */
+
+#include <linux/mutex.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include <linux/pm_domain.h>
+#include <linux/pm_opp.h>
+#include <linux/slab.h>
+
+#include <soc/tegra/common.h>
+
+static struct lock_class_key tegra_core_domain_lock_class;
+static bool tegra_core_domain_state_synced;
+static DEFINE_MUTEX(tegra_core_lock);
+
+bool tegra_soc_core_domain_state_synced(void)
+{
+ return tegra_core_domain_state_synced;
+}
+
+static int tegra_genpd_set_performance_state(struct generic_pm_domain *genpd,
+ unsigned int level)
+{
+ struct dev_pm_opp *opp;
+ int err;
+
+ opp = dev_pm_opp_find_level_ceil(&genpd->dev, &level);
+ if (IS_ERR(opp)) {
+ dev_err(&genpd->dev, "failed to find OPP for level %u: %pe\n",
+ level, opp);
+ return PTR_ERR(opp);
+ }
+
+ mutex_lock(&tegra_core_lock);
+ err = dev_pm_opp_set_opp(&genpd->dev, opp);
+ mutex_unlock(&tegra_core_lock);
+
+ dev_pm_opp_put(opp);
+
+ if (err) {
+ dev_err(&genpd->dev, "failed to set voltage to %duV: %d\n",
+ level, err);
+ return err;
+ }
+
+ return 0;
+}
+
+static unsigned int
+tegra_genpd_opp_to_performance_state(struct generic_pm_domain *genpd,
+ struct dev_pm_opp *opp)
+{
+ return dev_pm_opp_get_level(opp);
+}
+
+static int tegra_core_domain_probe(struct platform_device *pdev)
+{
+ struct generic_pm_domain *genpd;
+ const char *rname = "power";
+ int err;
+
+ genpd = devm_kzalloc(&pdev->dev, sizeof(*genpd), GFP_KERNEL);
+ if (!genpd)
+ return -ENOMEM;
+
+ genpd->name = pdev->dev.of_node->name;
+ genpd->set_performance_state = tegra_genpd_set_performance_state;
+ genpd->opp_to_performance_state = tegra_genpd_opp_to_performance_state;
+
+ err = devm_pm_opp_set_regulators(&pdev->dev, &rname, 1);
+ if (err)
+ return dev_err_probe(&pdev->dev, err,
+ "failed to set OPP regulator\n");
+
+ err = pm_genpd_init(genpd, NULL, false);
+ if (err) {
+ dev_err(&pdev->dev, "failed to init genpd: %d\n", err);
+ return err;
+ }
+
+ /*
+ * We have a "PMC -> Core" hierarchy of the power domains where
+ * PMC needs to resume and change performance (voltage) of the
+ * Core domain from the PMC GENPD on/off callbacks, hence we need
+ * to annotate the lock in order to remove confusion from the
+ * lockdep checker when a nested access happens.
+ */
+ lockdep_set_class(&genpd->mlock, &tegra_core_domain_lock_class);
+
+ err = of_genpd_add_provider_simple(pdev->dev.of_node, genpd);
+ if (err) {
+ dev_err(&pdev->dev, "failed to add genpd: %d\n", err);
+ goto remove_genpd;
+ }
+
+ return 0;
+
+remove_genpd:
+ pm_genpd_remove(genpd);
+
+ return err;
+}
+
+static void tegra_core_domain_set_synced(struct device *dev, bool synced)
+{
+ int err;
+
+ tegra_core_domain_state_synced = synced;
+
+ mutex_lock(&tegra_core_lock);
+ err = dev_pm_opp_sync_regulators(dev);
+ mutex_unlock(&tegra_core_lock);
+
+ if (err)
+ dev_err(dev, "failed to sync regulators: %d\n", err);
+}
+
+static void tegra_core_domain_sync_state(struct device *dev)
+{
+ tegra_core_domain_set_synced(dev, true);
+}
+
+static void tegra_core_domain_shutdown(struct platform_device *pdev)
+{
+ /*
+ * Ensure that core voltage is at a level suitable for boot-up
+ * before system is rebooted, which may be important for some
+ * devices if regulators aren't reset on reboot. This is usually
+ * the case if PMC soft-reboot is used.
+ */
+ tegra_core_domain_set_synced(&pdev->dev, false);
+}
+
+static const struct of_device_id tegra_core_domain_match[] = {
+ { .compatible = "nvidia,tegra20-core-domain", },
+ { .compatible = "nvidia,tegra30-core-domain", },
+ { }
+};
+
+static struct platform_driver tegra_core_domain_driver = {
+ .driver = {
+ .name = "tegra-core-power",
+ .of_match_table = tegra_core_domain_match,
+ .suppress_bind_attrs = true,
+ .sync_state = tegra_core_domain_sync_state,
+ },
+ .probe = tegra_core_domain_probe,
+ .shutdown = tegra_core_domain_shutdown,
+};
+builtin_platform_driver(tegra_core_domain_driver);
diff --git a/include/soc/tegra/common.h b/include/soc/tegra/common.h
index e8eab13aa199..9a4ac3af2401 100644
--- a/include/soc/tegra/common.h
+++ b/include/soc/tegra/common.h
@@ -22,6 +22,7 @@ struct tegra_core_opp_params {
#ifdef CONFIG_ARCH_TEGRA
bool soc_is_tegra(void);
+bool tegra_soc_core_domain_state_synced(void);
int devm_tegra_core_dev_init_opp_table(struct device *dev,
struct tegra_core_opp_params *params);
#else
@@ -30,6 +31,11 @@ static inline bool soc_is_tegra(void)
return false;
}
+static inline bool tegra_soc_core_domain_state_synced(void)
+{
+ return false;
+}
+
static inline int
devm_tegra_core_dev_init_opp_table(struct device *dev,
struct tegra_core_opp_params *params)
--
2.30.2
