On Wed, Mar 10, 2021 at 08:20:28PM +0530, Sameer Pujar wrote: > If I read this correctly below is the configuration you need, > SoC -> MCLK(fixed rate) -> PLL(wm8904) -> PLL output (256 * fs) -> sysclk For this device for integration with something like simple-audio-card since there's limited flexibility within the device the simplest thing would be to not make the internal clocking of the device visible and just have it figure out how to use the input clock, using the MCLK directly if possible otherwise using the FLL to generate a suitable clock. The trick is figuring out if it's best to vary the input clock or to use the FLL to adapt a fixed input clock, and of course adapting any existing users if things get changed.
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