On 3/8/21 10:32 AM, Sowjanya Komatineni wrote:
On 3/7/21 8:37 PM, Sudeep Holla wrote:
On Wed, Mar 03, 2021 at 10:08:10PM -0800, Sowjanya Komatineni wrote:
This patch adds cpu-idle-states and corresponding state nodes to
Tegra194 CPU in dt-binding document
I see that this platform has PSCI support. Can you care to explain why
you need additional DT bindings and driver for PSCI based CPU suspend.
Until the reasons are convincing, consider NACK from my side for this
driver and DT bindings. You should be really using those bindings and
the driver may be with minor changes there.
MCE firmware is in charge of state transition for Tegra194 carmel CPUs.
For run-time state transitions, need to provide state request along
with its residency time to MCE firmware which is running in the
background.
State min residency is updated into power_state value along with state
id that is passed to psci_cpu_suspend_enter
Also states cross-over idle times need to be provided to MCE firmware.
MCE firmware decides on state transition based on these inputs along
with its background work load.
So, Tegra specific CPU idle driver is required mainly to provide
cross-over thresholds from DT and run time idle state information to
MCE firmware through Tegra MCE communication APIs.
Allowing cross-over threshold through DT allows users to vary idle
time thresholds for state transitions based on different use-cases.
Hi Sudeep,
Can you please let me know if you have any more concerns for having this
Tegra specific cpuidle driver?
Thanks
Sowjanya
