On 05/03/21 11:11 am, Aswath Govindraju wrote: > According to latest errata of J721e [1], HS400 mode is not supported > in MMCSD0 subsystem (i2024) and SDR104 mode is not supported in MMCSD1/2 > subsystems (i2090). Therefore, replace mmc-hs400-1_8v with mmc-hs200-1_8v > in MMCSD0 subsystem and add a sdhci mask to disable SDR104 speed mode. > > Also, update the itap delay values for all the MMCSD subsystems according > the latest J721e data sheet[2] > > [1] - https://www.ti.com/lit/er/sprz455/sprz455.pdf > [2] - https://www.ti.com/lit/ds/symlink/tda4vm.pdf > > Fixes: cd48ce86a4d0 ("arm64: dts: ti: k3-j721e-common-proc-board: Add support for SD card UHS modes") > Signed-off-by: Aswath Govindraju <a-govindraju@xxxxxx> Reviewed-by: Kishon Vijay Abraham I <kishon@xxxxxx> > --- > > Changes since v1: > - Corrected the fixes tag to latest commit that makes changes to the > sdhci DT nodes. > > arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 17 ++++++++++++++++- > 1 file changed, 16 insertions(+), 1 deletion(-) > > diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi > index 8c84dafb7125..f1e7da3dfa27 100644 > --- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi > +++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi > @@ -1042,13 +1042,16 @@ > assigned-clocks = <&k3_clks 91 1>; > assigned-clock-parents = <&k3_clks 91 2>; > bus-width = <8>; > - mmc-hs400-1_8v; > + mmc-hs200-1_8v; > mmc-ddr-1_8v; > ti,otap-del-sel-legacy = <0xf>; > ti,otap-del-sel-mmc-hs = <0xf>; > ti,otap-del-sel-ddr52 = <0x5>; > ti,otap-del-sel-hs200 = <0x6>; > ti,otap-del-sel-hs400 = <0x0>; > + ti,itap-del-sel-legacy = <0x10>; > + ti,itap-del-sel-mmc-hs = <0xa>; > + ti,itap-del-sel-ddr52 = <0x3>; > ti,trm-icp = <0x8>; > ti,strobe-sel = <0x77>; > dma-coherent; > @@ -1069,9 +1072,15 @@ > ti,otap-del-sel-sdr25 = <0xf>; > ti,otap-del-sel-sdr50 = <0xc>; > ti,otap-del-sel-ddr50 = <0xc>; > + ti,itap-del-sel-legacy = <0x0>; > + ti,itap-del-sel-sd-hs = <0x0>; > + ti,itap-del-sel-sdr12 = <0x0>; > + ti,itap-del-sel-sdr25 = <0x0>; > + ti,itap-del-sel-ddr50 = <0x2>; > ti,trm-icp = <0x8>; > ti,clkbuf-sel = <0x7>; > dma-coherent; > + sdhci-caps-mask = <0x2 0x0>; > }; > > main_sdhci2: mmc@4f98000 { > @@ -1089,9 +1098,15 @@ > ti,otap-del-sel-sdr25 = <0xf>; > ti,otap-del-sel-sdr50 = <0xc>; > ti,otap-del-sel-ddr50 = <0xc>; > + ti,itap-del-sel-legacy = <0x0>; > + ti,itap-del-sel-sd-hs = <0x0>; > + ti,itap-del-sel-sdr12 = <0x0>; > + ti,itap-del-sel-sdr25 = <0x0>; > + ti,itap-del-sel-ddr50 = <0x2>; > ti,trm-icp = <0x8>; > ti,clkbuf-sel = <0x7>; > dma-coherent; > + sdhci-caps-mask = <0x2 0x0>; > }; > > usbss0: cdns-usb@4104000 { >
