On Tue, Mar 9, 2021 at 12:14 PM Linus Walleij <linus.walleij@xxxxxxxxxx> wrote:
>
> On Mon, Mar 8, 2021 at 10:13 PM Rob Herring <robh@xxxxxxxxxx> wrote:
> > On Mon, Mar 08, 2021 at 09:29:54PM +0100, Arnd Bergmann wrote:
>
> > > This is obviously more work for the drivers, but at least it keeps
> > > the common code free of the hack while also allowing drivers to
> > > use ioremap_np() intentionally on other platforms.
> >
> > I don't agree. The problem is within the interconnect. The device and
> > its driver are unaware of this.
>
> If it is possible that a driver needs to use posted access on one
> SoC and nonposted on another SoC then clearly the nature
> of the access need to be part of the memory access abstraction,
> obviously ioremap() one way or another.
There are two possible scenarios:
- drivers that we already know are shared between apple and
other vendors (s3c-serial, pasemi i2c) would need to use
nonposted mmio on Apple but can use either one on other
platforms. On non-ARM CPUs, the ioremap_np() function
might fail when the hardware only supports posted writes.
- A driver writer may want to choose between posted and
nonposted mmio based on performance considerations:
if writes are never serialized, posted writes should always
be faster. However, if the driver uses a spinlock to serialize
writes, then a nonposted write is likely faster than a posted
write followed by a read that serializes the spin_unlock.
In this case we want the driver to explicitly pick one over
the other, and not have rely on bus specific magic.
> Having the driver conditionally use different ioremap_*
> functions depending on SoC seems awkward. We had different
> execution paths for OF and ACPI drivers and have been working
> hard to create fwnode to abstract this away for drivers used with
> both abstractions for example. If we can hide it from drivers
> from day 1 I think we can save maintenance costs in the long
> run.
>
> Given that the Apple silicon through it's heritage from Samsung
> S3C (the genealogy is unclear to me) already share drivers with
> this platform, this seems to already be the case so it's not a
> theoretical use case.
As far as I can tell, there are only a handful of soc specific drivers
that are actually shared with other platforms. Aside from serial
and i2c, these are the ones that I can see being shared:
- there is an on-chip nvme host controller that is not PCI. So far,
nobody else does this, but it can clearly happen in the future
- I think one of the USB controllers is a standard designware
part, while the others are PCI devices.
- The PCI host bridge may be close enough to the standard
that we can use the generic driver for config space access.
Arnd
