Quoting Konrad Dybcio (2021-02-20 07:56:16)
> Downstream kernel executes a bunch of commands, such as keeping
> GPU/MMSS interface clocks alive to make sure all subsystems can
> work properly. Add these to make sure they do.
>
> Fixes: f2a76a2955c0 ("clk: qcom: Add Global Clock controller (GCC) driver for SDM660")
> Signed-off-by: Konrad Dybcio <konrad.dybcio@xxxxxxxxxxxxxx>
> ---
> drivers/clk/qcom/gcc-sdm660.c | 23 ++++++++++++++++++++++-
> 1 file changed, 22 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/clk/qcom/gcc-sdm660.c b/drivers/clk/qcom/gcc-sdm660.c
> index bc8dfcd6d629..db2185c88b77 100644
> --- a/drivers/clk/qcom/gcc-sdm660.c
> +++ b/drivers/clk/qcom/gcc-sdm660.c
> @@ -11,6 +11,7 @@
> #include <linux/module.h>
> #include <linux/of.h>
> #include <linux/of_device.h>
> +#include <linux/clk.h>
> #include <linux/clk-provider.h>
> #include <linux/regmap.h>
> #include <linux/reset-controller.h>
> @@ -2622,7 +2623,27 @@ static int gcc_sdm660_probe(struct platform_device *pdev)
> if (ret)
> return ret;
>
> - return qcom_cc_really_probe(pdev, &gcc_sdm660_desc, regmap);
> + ret = qcom_cc_really_probe(pdev, &gcc_sdm660_desc, regmap);
> + if (ret)
> + return ret;
> +
> + /* Disable the GPLL0 active input to MMSS and GPU via MISC registers */
> + regmap_update_bits(regmap, 0x0902c, 0x3, 0x3);
> + regmap_update_bits(regmap, 0x71028, 0x3, 0x3);
> +
> + /* This clock is used for all MMSSCC register access */
> + clk_prepare_enable(gcc_mmss_noc_cfg_ahb_clk.clkr.hw.clk);
> +
> + /* This clock is used for all GPUCC register access */
> + clk_prepare_enable(gcc_gpu_cfg_ahb_clk.clkr.hw.clk);
> +
> + /* Keep bimc gfx clock port on all the time */
> + clk_prepare_enable(gcc_bimc_gfx_clk.clkr.hw.clk);
> +
Preferably just set these various bits with regmap_update_bits() during
probe. Also, please do it before regsitering the clks, not after.
> + /* Set the HMSS_GPLL0_SRC for 300MHz to CPU subsystem */
> + clk_set_rate(hmss_gpll0_clk_src.clkr.hw.clk, 300000000);
Is this not already the case?
> +
> + return ret;
> }
>
