Il 08/02/21 19:21, Stephen Boyd ha scritto:
Quoting AngeloGioacchino Del Regno (2021-01-14 14:10:55)
The pixel and byte clocks rate should not be cached, as a VCO shutdown
may clear the frequency setup and this may not be set again due to the
cached rate being present.
This will also be useful when shadow clocks will be implemented in
the DSI PLL for seamless timing/resolution switch.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@xxxxxxxxxxxxxx>
---
drivers/clk/qcom/mmcc-msm8998.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
We didn't do this on sdm845, so I'm not going to apply this patch. The
rate caching thing is a problem with the display driver that should be
fixed some other way vs. setting nocache here.
Ok, I agree.
