On Fri, 05 Feb 2021 15:58:14 +0900, Damien Le Moal wrote: > The Canaan Kendryte K210 SoC CPU cores are based on a rocket chip > version using a draft verion of the RISC-V ISA specifications. To avoid > any confusion with CPU cores using stable specifications, add the > compatible string "canaan,k210" for this SoC CPU cores. > > Also add the "riscv,none" value to the mmu-type property to allow a DT > to indicate that the CPU being described does not have an MMU or that > it has an MMU that is not usable (which is the case for the K210 SoC). > > Cc: Paul Walmsley <paul.walmsley@xxxxxxxxxx> > Cc: Rob Herring <robh@xxxxxxxxxx> > Cc: devicetree@xxxxxxxxxxxxxxx > Signed-off-by: Damien Le Moal <damien.lemoal@xxxxxxx> > Reviewed-by: Atish Patra <atish.patra@xxxxxxx> > Reviewed-by: Anup Patel <anup@xxxxxxxxxxxxxx> > --- > Documentation/devicetree/bindings/riscv/cpus.yaml | 2 ++ > 1 file changed, 2 insertions(+) > Acked-by: Rob Herring <robh@xxxxxxxxxx>
