On Wed, Feb 3, 2021 at 6:29 PM Damien Le Moal <damien.lemoal@xxxxxxx> wrote: > > The Canaan Kendryte K210 SoC CPU cores are based on a rocket chip > version using a draft verion of the RISC-V ISA specifications. To avoid > any confusion with CPU cores using stable specifications, add the > compatible string "canaan,k210" for this SoC CPU cores. > > Also add the "riscv,none" value to the mmu-type property to allow a DT > to indicate that the CPU being described does not have an MMU or that > it has an MMU that is not usable (which is the case for the K210 SoC). > > Cc: Paul Walmsley <paul.walmsley@xxxxxxxxxx> > Cc: Rob Herring <robh@xxxxxxxxxx> > Cc: devicetree@xxxxxxxxxxxxxxx > Signed-off-by: Damien Le Moal <damien.lemoal@xxxxxxx> > Reviewed-by: Atish Patra <atish.patra@xxxxxxx> Looks good to me. Reviewed-by: Anup Patel <anup@xxxxxxxxxxxxxx> Regards, Anup > --- > Documentation/devicetree/bindings/riscv/cpus.yaml | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml > index eb6843f69f7c..e534f6a7cfa1 100644 > --- a/Documentation/devicetree/bindings/riscv/cpus.yaml > +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml > @@ -39,6 +39,7 @@ properties: > - sifive,u74 > - sifive,u5 > - sifive,u7 > + - canaan,k210 > - const: riscv > - const: riscv # Simulator only > description: > @@ -56,6 +57,7 @@ properties: > - riscv,sv32 > - riscv,sv39 > - riscv,sv48 > + - riscv,none > > riscv,isa: > description: > -- > 2.29.2 > > > _______________________________________________ > linux-riscv mailing list > linux-riscv@xxxxxxxxxxxxxxxxxxx > http://lists.infradead.org/mailman/listinfo/linux-riscv
