From: Brian Masney <masneyb@xxxxxxxxxxxxx> Add support for the a3xx GPU Signed-off-by: Brian Masney <masneyb@xxxxxxxxxxxxx> Signed-off-by: Iskren Chernev <iskren.chernev@xxxxxxxxx> Tested-by: Alexey Minnekhanov <alexeymin@xxxxxxxxxxxxxxxx> Reviewed-by: Brian Masney <masneyb@xxxxxxxxxxxxx> --- Changes in v2: - base set to next-20210122 - add tags from v1 replies - add Signed-off-by: me on first three patches - add commit message to 2nd patch v1: https://lkml.org/lkml/2020/12/30/322 arch/arm/boot/dts/qcom-msm8974.dtsi | 45 +++++++++++++++++++++++++++++ 1 file changed, 45 insertions(+) diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi index 51f5f904f9eb9..c399446d8154e 100644 --- a/arch/arm/boot/dts/qcom-msm8974.dtsi +++ b/arch/arm/boot/dts/qcom-msm8974.dtsi @@ -1399,6 +1399,51 @@ cnoc: interconnect@fc480000 { <&rpmcc RPM_SMD_CNOC_A_CLK>; }; + gpu_opp_table: opp_table { + status = "disabled"; + + compatible = "operating-points-v2"; + + opp-800000000 { + opp-hz = /bits/ 64 <800000000>; + }; + + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + }; + + opp-275000000 { + opp-hz = /bits/ 64 <275000000>; + }; + }; + + gpu: adreno@fdb00000 { + status = "disabled"; + + compatible = "qcom,adreno-330.2", + "qcom,adreno"; + reg = <0xfdb00000 0x10000>; + reg-names = "kgsl_3d0_reg_memory"; + interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "kgsl_3d0_irq"; + clock-names = "core", + "iface", + "mem_iface"; + clocks = <&mmcc OXILI_GFX3D_CLK>, + <&mmcc OXILICX_AHB_CLK>, + <&mmcc OXILICX_AXI_CLK>; + sram = <&gmu_sram>; + power-domains = <&mmcc OXILICX_GDSC>; + operating-points-v2 = <&gpu_opp_table>; + + interconnects = <&mmssnoc MNOC_MAS_GRAPHICS_3D &bimc BIMC_SLV_EBI_CH0>, + <&ocmemnoc OCMEM_VNOC_MAS_GFX3D &ocmemnoc OCMEM_SLV_OCMEM>; + interconnect-names = "gfx-mem", + "ocmem"; + + // iommus = <&gpu_iommu 0>; + }; + mdss: mdss@fd900000 { status = "disabled"; base-commit: 226871e2eda4832d94c3239add7e52ad17b81ce5 -- 2.30.0
