On Thu, Jan 21, 2021 at 07:33:54PM -0600, Samuel Holland wrote:
> On 1/21/21 2:35 PM, Marc Zyngier wrote:
> > On Sun, 17 Jan 2021 23:50:30 -0600, Samuel Holland wrote:
> >> Allwinner sun6i/sun8i/sun50i SoCs (A31 and newer) have two interrupt
> >> controllers: GIC and R_INTC. GIC does not support wakeup. R_INTC handles
> >> the external NMI pin, and provides 32+ IRQs to the ARISC. The first 16
> >> of these correspond 1:1 to a block of GIC IRQs starting with the NMI.
> >> The last 13-16 multiplex the first (up to) 128 GIC SPIs.
> >>
> >> This series replaces the existing chained irqchip driver that could only
> >> control the NMI, with a stacked irqchip driver that also provides wakeup
> >> capability for those multiplexed SPI IRQs. The idea is to preconfigure
> >> the ARISC's IRQ controller, and then the ARISC firmware knows to wake up
> >> as soon as it receives an IRQ. It can also decide how deep it can
> >> suspend based on the enabled wakeup IRQs.
> >>
> >> [...]
> >
> > Applied to irq/irqchip-5.12, thanks!
> >
> > [01/10] dt-bindings: irq: sun6i-r: Split the binding from sun7i-nmi
> > commit: ad6b47cdef760410311f41876b21eb0c6fda4717
> > [02/10] dt-bindings: irq: sun6i-r: Add a compatible for the H3
> > commit: 6436eb4417094ea3308b33d8392fc02a1068dc78
> > [03/10] irqchip/sun6i-r: Use a stacked irqchip driver
> > commit: 4e34614636b31747b190488240a95647c227021f
> > [04/10] irqchip/sun6i-r: Add wakeup support
> > commit: 7ab365f6cd6de1e2b0cb1e1e3873dbf68e6f1003
> >
> > Please route the dts patches via the soc tree. Also, I had to
> > manually fix the first patch as it wouldn't apply on top of
> > 5.11-rc4 (which tree has it been diffed against?). Please
> > check that the resolution is correct.
>
> This series was based on sunxi/for-next, which contains commit
> 752b0aac99c7 ("dt-bindings: irq: sun7i-nmi: Add binding documentation
> for the V3s NMI")[1].
I assume merging the DT bits alone would break things? If so, I guess we
can wait for 5.12 to be released before merging it
Maxime
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