Document the Sparx5 reset device driver bindings The driver uses two syscons on sparx5 for access to the reset control and the reset status. Signed-off-by: Steen Hegelund <steen.hegelund@xxxxxxxxxxxxx> --- .../bindings/reset/microchip,rst.yaml | 59 +++++++++++++++++++ 1 file changed, 59 insertions(+) create mode 100644 Documentation/devicetree/bindings/reset/microchip,rst.yaml diff --git a/Documentation/devicetree/bindings/reset/microchip,rst.yaml b/Documentation/devicetree/bindings/reset/microchip,rst.yaml new file mode 100644 index 000000000000..af01016e246f --- /dev/null +++ b/Documentation/devicetree/bindings/reset/microchip,rst.yaml @@ -0,0 +1,59 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/reset/microchip,rst.yaml#"; +$schema: "http://devicetree.org/meta-schemas/core.yaml#"; + +title: Microchip Sparx5 Switch Reset Controller + +maintainers: + - Steen Hegelund <steen.hegelund@xxxxxxxxxxxxx> + - Lars Povlsen <lars.povlsen@xxxxxxxxxxxxx> + +description: | + The Microchip Sparx5 Switch provides reset control and implements the following + functions + - One Time Switch Core Reset (Soft Reset) + +properties: + $nodename: + pattern: "^reset-controller@[0-9a-f]+$" + + compatible: + const: microchip,sparx5-switch-reset + + reg: + maxItems: 1 + + "#reset-cells": + const: 1 + + cpu-syscon: + $ref: "/schemas/types.yaml#/definitions/phandle" + description: syscon used to access CPU reset + maxItems: 1 + + gcb-syscon: + $ref: "/schemas/types.yaml#/definitions/phandle" + description: syscon used to access Global Control Block + maxItems: 1 + +required: + - compatible + - reg + - "#reset-cells" + - cpu-syscon + - gcb-syscon + +additionalProperties: false + +examples: + - | + reset: reset-controller@0 { + compatible = "microchip,sparx5-switch-reset"; + reg = <0x0 0x0>; + #reset-cells = <1>; + cpu-syscon = <&cpu_ctrl>; + gcb-syscon = <&gcb_ctrl>; + }; + -- 2.29.2
