On Tue, Jan 19, 2021 at 10:39:25AM -0600, Dave Gerlach wrote: > The AM642 SoC belongs to the K3 Multicore SoC architecture platform, > providing advanced system integration to enable applications such as > Motor Drives, PLC, Remote IO and IoT Gateways. > > Some highlights of this SoC are: > * Dual Cortex-A53s in a single cluster, two clusters of dual Cortex-R5F > MCUs, and a single Cortex-M4F. > * Two Gigabit Industrial Communication Subsystems (ICSSG). > * Integrated Ethernet switch supporting up to a total of two external > ports. > * PCIe-GEN2x1L, USB3/USB2, 2xCAN-FD, eMMC and SD, UFS, OSPI memory > controller, QSPI, I2C, eCAP/eQEP, ePWM, ADC, among other > peripherals. > * Centralized System Controller for Security, Power, and Resource > Management (DMSC). > > See AM64X Technical Reference Manual (SPRUIM2, Nov 2020) > for further details: https://www.ti.com/lit/pdf/spruim2 > > Introduce basic support for the AM642 SoC to enable ramdisk or MMC > boot. Introduce the sdhci, i2c, spi, and uart MAIN domain periperhals > under cbass_main and the i2c, spi, and uart MCU domain periperhals > under cbass_mcu. > > Signed-off-by: Faiz Abbas <faiz_abbas@xxxxxx> > Signed-off-by: Aswath Govindraju <a-govindraju@xxxxxx> > Signed-off-by: Dave Gerlach <d-gerlach@xxxxxx> > --- > v1 -> v2: > * Add i2c. sdhci. and spi nodes to cbass_main > * Add cbass_mcu with uart, i2c, and spi nodes > * Add oc_sram node > * Add additional ranges for main_cbass to cover all use cases. > > arch/arm64/boot/dts/ti/k3-am64-main.dtsi | 332 +++++++++++++++++++++++ > arch/arm64/boot/dts/ti/k3-am64-mcu.dtsi | 76 ++++++ > arch/arm64/boot/dts/ti/k3-am64.dtsi | 103 +++++++ > arch/arm64/boot/dts/ti/k3-am642.dtsi | 65 +++++ > 4 files changed, 576 insertions(+) > create mode 100644 arch/arm64/boot/dts/ti/k3-am64-main.dtsi > create mode 100644 arch/arm64/boot/dts/ti/k3-am64-mcu.dtsi > create mode 100644 arch/arm64/boot/dts/ti/k3-am64.dtsi > create mode 100644 arch/arm64/boot/dts/ti/k3-am642.dtsi > > diff --git a/arch/arm64/boot/dts/ti/k3-am64.dtsi b/arch/arm64/boot/dts/ti/k3-am64.dtsi > new file mode 100644 > index 000000000000..a35a0aff50f8 > --- /dev/null > +++ b/arch/arm64/boot/dts/ti/k3-am64.dtsi > @@ -0,0 +1,103 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * Device Tree Source for AM642 SoC Family > + * > + * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/ > + */ > + > +#include <dt-bindings/gpio/gpio.h> > +#include <dt-bindings/interrupt-controller/irq.h> > +#include <dt-bindings/interrupt-controller/arm-gic.h> > +#include <dt-bindings/pinctrl/k3.h> > +#include <dt-bindings/soc/ti,sci_pm_domain.h> > + > +/ { > + model = "Texas Instruments K3 AM642 SoC"; > + compatible = "ti,am642"; > + interrupt-parent = <&gic500>; > + #address-cells = <2>; > + #size-cells = <2>; > + > + aliases { > + serial0 = &mcu_uart0; > + serial1 = &mcu_uart1; > + serial2 = &main_uart0; > + serial3 = &main_uart1; > + serial4 = &main_uart2; > + serial5 = &main_uart3; > + serial6 = &main_uart4; > + serial7 = &main_uart5; > + serial8 = &main_uart6; > + }; > + > + chosen { }; > + > + firmware { > + optee { > + compatible = "linaro,optee-tz"; > + method = "smc"; > + }; > + > + psci: psci { > + compatible = "arm,psci-1.0"; > + method = "smc"; > + }; > + }; > + > + a53_timer0: timer-cl0-cpu0 { > + compatible = "arm,armv8-timer"; > + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* cntpsirq */ > + <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* cntpnsirq */ > + <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* cntvirq */ > + <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* cnthpirq */ > + }; > + > + pmu: pmu { > + compatible = "arm,armv8-pmuv3"; Is this just copy paste from some DTS or do we really don't know which CPU this platform has 😄 ? Reading further down, I thought it was Cortex A53, no ? -- Regards, Sudeep
