On Mon, 11 Jan 2021 23:59:41 -0600, Samuel Holland wrote: > The R_INTC in the A31 and newer sun8i/sun50i SoCs has additional > functionality compared to the sun7i/sun9i NMI controller. Among other > things, it multiplexes access to up to 128 interrupts corresponding to > (and in parallel to) the first 128 GIC SPIs. This means the NMI is no > longer the lowest-numbered hwirq at this irqchip, since it is SPI 32 or > 96 (depending on SoC). hwirq 0 now corresponds to SPI 0, usually UART0. > > To allow access to all multiplexed IRQs, the R_INTC requires a new > binding where the interrupt number matches the GIC interrupt number. > Otherwise, interrupts with hwirq numbers below the NMI would not be > representable in the device tree. > > For simplicity, copy the three-cell GIC binding; this disambiguates > interrupt 0 in the old binding (the NMI) from interrupt 0 in the new > binding (SPI 0) by the number of cells. > > Because the H6 R_INTC has a different mapping from multiplexed IRQs to > top-level register bits, it is no longer compatible with the A31 R_INTC. > > Signed-off-by: Samuel Holland <samuel@xxxxxxxxxxxx> > --- > .../allwinner,sun6i-a31-r-intc.yaml | 66 +++++++++++++++++++ > .../allwinner,sun7i-a20-sc-nmi.yaml | 10 --- > 2 files changed, 66 insertions(+), 10 deletions(-) > create mode 100644 Documentation/devicetree/bindings/interrupt-controller/allwinner,sun6i-a31-r-intc.yaml > Reviewed-by: Rob Herring <robh@xxxxxxxxxx>
