On Thu 14 Jan 11:47 CST 2021, AngeloGioacchino Del Regno wrote:
> The SDM660 SoC uses the same configuration as MSM8996, but the
> clock scheme uses a differential reference clock and none of
> the SoCs in this series (630, 636 and others) have got a usable
> PHY_CLK_SCHEME register in the TCSR for clk scheme detection.
>
Reviewed-by: Bjorn Andersson <bjorn.andersson@xxxxxxxxxx>
> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@xxxxxxxxxxxxxx>
> ---
> drivers/phy/qualcomm/phy-qcom-qusb2.c | 16 ++++++++++++++++
> 1 file changed, 16 insertions(+)
>
> diff --git a/drivers/phy/qualcomm/phy-qcom-qusb2.c b/drivers/phy/qualcomm/phy-qcom-qusb2.c
> index 8fcfea2a8f1f..3629f60460a1 100644
> --- a/drivers/phy/qualcomm/phy-qcom-qusb2.c
> +++ b/drivers/phy/qualcomm/phy-qcom-qusb2.c
> @@ -289,6 +289,19 @@ static const struct qusb2_phy_cfg qusb2_v2_phy_cfg = {
> .update_tune1_with_efuse = true,
> };
>
> +static const struct qusb2_phy_cfg sdm660_phy_cfg = {
> + .tbl = msm8996_init_tbl,
> + .tbl_num = ARRAY_SIZE(msm8996_init_tbl),
> + .regs = msm8996_regs_layout,
> +
> + .has_pll_test = true,
> + .se_clk_scheme_default = false,
> + .disable_ctrl = (CLAMP_N_EN | FREEZIO_N | POWER_DOWN),
> + .mask_core_ready = PLL_LOCKED,
> + .autoresume_en = BIT(3),
> +};
> +
> +
> static const char * const qusb2_phy_vreg_names[] = {
> "vdda-pll", "vdda-phy-dpdm",
> };
> @@ -829,6 +842,9 @@ static const struct of_device_id qusb2_phy_of_match_table[] = {
> }, {
> .compatible = "qcom,msm8998-qusb2-phy",
> .data = &msm8998_phy_cfg,
> + }, {
> + .compatible = "qcom,sdm660-qusb2-phy",
> + .data = &sdm660_phy_cfg,
> }, {
> /*
> * Deprecated. Only here to support legacy device
> --
> 2.29.2
>
