On Mon, Jan 11, 2021 at 11:59:40PM -0600, Samuel Holland wrote: > Allwinner sun6i/sun8i/sun50i SoCs (A31 and newer) have two interrupt > controllers: GIC and R_INTC. GIC does not support wakeup. R_INTC handles > the external NMI pin, and provides 32+ IRQs to the ARISC. The first 16 > of these correspond 1:1 to a block of GIC IRQs starting with the NMI. > The last 13-16 multiplex the first (up to) 128 GIC SPIs. > > This series replaces the existing chained irqchip driver that could only > control the NMI, with a stacked irqchip driver that also provides wakeup > capability for those multiplexed SPI IRQs. The idea is to preconfigure > the ARISC's IRQ controller, and then the ARISC firmware knows to wake up > as soon as it receives an IRQ. It can also decide how deep it can > suspend based on the enabled wakeup IRQs. > > As future work, it may be useful to do the chained->stacked conversion > on the sunxi-nmi driver as well. > > Patches 1-2 add the new bindings. > Patch 3 adds the new driver. > Patch 4 adds wakeup capability. > Remaining patches update the device trees to use R_INTC where beneficial. > > With appropriate firmware and configuration, this series allows waking > from (and it has been tested with) the RTC, NMI/PMIC (power button, A/C > plug, etc.), all GPIO ports (button, lid switch, modem, etc.), LRADC, > and UARTs. I have tested this patch set on the H3, A64, H5, and H6 SoCs. Acked-by: Maxime Ripard <mripard@xxxxxxxxxx> Thanks! Maxime
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