On Tue, Jan 12, 2021 at 2:56 AM Zhen Lei <thunder.leizhen@xxxxxxxxxx> wrote: > +--- > +$id: http://devicetree.org/schemas/arm/hisilicon/l3cache.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Hisilicon L3 cache controller > + > +maintainers: > + - Wei Xu <xuwei5@xxxxxxxxxxxxx> > + > +description: | > + The Hisilicon L3 outer cache controller supports a maximum of 36-bit physical > + addresses. The data cached in the L3 outer cache can be operated based on the > + physical address range or the entire cache. > + > +properties: > + compatible: > + items: > + - const: hisilicon,l3cache > + The compatible string needs to be a little more specific, I'm sure you cannot guarantee that this is the only L3 cache controller ever designed in the past or future by HiSilicon. Normally when you have an IP block that is itself unnamed but that is specific to one or a few SoCs but that has no na, the convention is to include the name of the first SoC that contained it. Can you share which products actually use this L3 cache controller? On a related note, what does the memory map look like on this chip? Do you support more than 4GB of total installed memory? If you do, this becomes a problem in the future as highmem support winds down. In fact anything more than 1GB on a 32-bit system requires more work on the kernel to be completed before we remove highmem, and will incur a slowdown. If the total is under 4GB but the memory is not in a contiguous physical address range. See my Linaro connect presentation[1] for further information on the topic. Arnd [1] https://connect.linaro.org/resources/lvc20/lvc20-106/
