On Wed, Dec 30, 2020 at 10:22:02PM +0100, Bert Vermeulen wrote: > The RTL838x/839x family of SoCs are Realtek switches with an embedded > MIPS core. > > * RTL838x - 500MHz 4kce single core - 1Gbit ports and L2 features > * RTL839x - 700MHz 34Kc single core - 1Gbit ports and L2 features > > These switches, depending on the exact part number, will have anywhere > between 8 and 50 ports. The MIPS core is wired to a switch cpu port which > has a tagging feature allowing us to make use of the DSA subsystem. > The SoCs are somewhat basic in certain areas, getting better with more > advanced features on newer series. > > The switch functionality is MMIO-mapped via a large MFD region. > > The SoCs have the following peripherals > * ethernet > * switch > * uart - ns16550a > * spi-flash interface > * gpio > * wdt > * led > > The code was derived from various vendor SDKs based on Linux v2.6 > kernels. > > This patchset allows us to boot RTL838x/RTL839x units with basic support. > Most of the other drivers are already written and functional, and work to > get them upstream is already in progress. > > Signed-off-by: Birger Koblitz <mail@xxxxxxxxxxxxxxxxx> > Signed-off-by: Bert Vermeulen <bert@xxxxxxxx> > Signed-off-by: John Crispin <john@xxxxxxxxxxx> > Signed-off-by: Sander Vanheule <sander@xxxxxxxxxxxxx> > --- > .../devicetree/bindings/mips/realtek-rtl.yaml | 24 ++++++ Generally, this should be a separate patch. > arch/mips/boot/dts/Makefile | 1 + > arch/mips/boot/dts/realtek/rtl838x.dtsi | 21 +++++ > arch/mips/boot/dts/realtek/rtl839x.dtsi | 21 +++++ > arch/mips/boot/dts/realtek/rtl83xx.dtsi | 83 +++++++++++++++++++ > 5 files changed, 150 insertions(+) > create mode 100644 Documentation/devicetree/bindings/mips/realtek-rtl.yaml > create mode 100644 arch/mips/boot/dts/realtek/rtl838x.dtsi > create mode 100644 arch/mips/boot/dts/realtek/rtl839x.dtsi > create mode 100644 arch/mips/boot/dts/realtek/rtl83xx.dtsi > > diff --git a/Documentation/devicetree/bindings/mips/realtek-rtl.yaml b/Documentation/devicetree/bindings/mips/realtek-rtl.yaml > new file mode 100644 > index 000000000000..aadff8ce0f49 > --- /dev/null > +++ b/Documentation/devicetree/bindings/mips/realtek-rtl.yaml > @@ -0,0 +1,24 @@ > +# SPDX-License-Identifier: GPL-2.0-or-later OR BSD-2-Clause > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/mips/realtek-rtl.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Realtek RTL83xx/93xx SoC series device tree bindings > + > +maintainers: > + - Bert Vermeulen <bert@xxxxxxxx> > + - Sander Vanheule <sander@xxxxxxxxxxxxx> > + > +properties: > + $nodename: > + const: "/" > + compatible: > + oneOf: > + # RTL8382-based boards > + - items: > + - enum: > + - cisco,sg220-26 > + - const: realtek,rtl8382-soc > + > +additionalProperties: true > diff --git a/arch/mips/boot/dts/Makefile b/arch/mips/boot/dts/Makefile > index 0259238d7a2e..60bd7d2a9ad8 100644 > --- a/arch/mips/boot/dts/Makefile > +++ b/arch/mips/boot/dts/Makefile > @@ -14,6 +14,7 @@ subdir-$(CONFIG_FIT_IMAGE_FDT_NI169445) += ni > subdir-$(CONFIG_MACH_PIC32) += pic32 > subdir-$(CONFIG_ATH79) += qca > subdir-$(CONFIG_RALINK) += ralink > +subdir-$(CONFIG_MACH_REALTEK_RTL) += realtek > subdir-$(CONFIG_FIT_IMAGE_FDT_XILFPGA) += xilfpga > > obj-$(CONFIG_BUILTIN_DTB) := $(addsuffix /, $(subdir-y)) > diff --git a/arch/mips/boot/dts/realtek/rtl838x.dtsi b/arch/mips/boot/dts/realtek/rtl838x.dtsi > new file mode 100644 > index 000000000000..6cc4ff5c0d19 > --- /dev/null > +++ b/arch/mips/boot/dts/realtek/rtl838x.dtsi > @@ -0,0 +1,21 @@ > +// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-2-Clause > + > +/ { > + cpus { > + #address-cells = <1>; > + #size-cells = <0>; > + > + cpu@0 { > + compatible = "mips,mips4KEc"; > + reg = <0>; > + clocks = <&baseclk 0>; > + clock-names = "cpu"; > + }; > + }; > + > + baseclk: baseclk { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + clock-frequency = <500000000>; > + }; > +}; > diff --git a/arch/mips/boot/dts/realtek/rtl839x.dtsi b/arch/mips/boot/dts/realtek/rtl839x.dtsi > new file mode 100644 > index 000000000000..2b5bad8fcf2f > --- /dev/null > +++ b/arch/mips/boot/dts/realtek/rtl839x.dtsi > @@ -0,0 +1,21 @@ > +// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-2-Clause > + > +/ { > + cpus { > + #address-cells = <1>; > + #size-cells = <0>; > + > + cpu@0 { > + compatible = "mips,mips34Kc"; > + reg = <0>; > + clocks = <&baseclk 0>; > + clock-names = "cpu"; > + }; > + }; > + > + baseclk: baseclk { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + clock-frequency = <500000000>; > + }; > +}; > diff --git a/arch/mips/boot/dts/realtek/rtl83xx.dtsi b/arch/mips/boot/dts/realtek/rtl83xx.dtsi > new file mode 100644 > index 000000000000..17fa90002e00 > --- /dev/null > +++ b/arch/mips/boot/dts/realtek/rtl83xx.dtsi > @@ -0,0 +1,83 @@ > +// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-2-Clause > + > +/ { > + #address-cells = <1>; > + #size-cells = <1>; > + > + aliases { > + serial0 = &uart0; > + serial1 = &uart1; > + }; > + > + cpuintc: cpuintc { > + compatible = "mti,cpu-interrupt-controller"; > + #address-cells = <0>; > + #interrupt-cells = <1>; > + interrupt-controller; > + }; > + > + soc { > + compatible = "simple-bus"; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0x0 0xb8000000 0x10000>; > + > + spi: spi@1200 { > + compatible = "realtek,rtl-spi"; Not documented. Needs to have an SoC specific compatible. > + reg = <0x1200 0x100>; > + > + #address-cells = <1>; > + #size-cells = <0>; > + > + status = "disabled"; > + }; > + > + uart0: uart@2000 { serial@2000 Build the dtb with W=1 and run 'make dtbs_check' and fix any warnings. The above issue should show up. > + compatible = "ns16550a"; No quirks for this? Best to have a more specific compatible in case you do. > + reg = <0x2000 0x100>; > + > + clock-frequency = <200000000>; > + > + interrupt-parent = <&intc>; > + interrupts = <31>; > + > + reg-io-width = <1>; > + reg-shift = <2>; > + fifo-size = <1>; > + no-loopback-test; > + > + status = "disabled"; > + }; > + > + uart1: uart@2100 { > + compatible = "ns16550a"; > + reg = <0x2100 0x100>; > + > + clock-frequency = <200000000>; > + > + interrupt-parent = <&intc>; > + interrupts = <30>; > + > + reg-io-width = <1>; > + reg-shift = <2>; > + fifo-size = <1>; > + no-loopback-test; > + > + status = "disabled"; > + }; > + > + intc: interrupt-controller@3000 { > + compatible = "realtek,rtl-intc"; Not documented. > + #interrupt-cells = <1>; > + interrupt-controller; > + reg = <0x3000 0x20>; > + }; > + }; > + > + switch_bus: switch-bus@bb000000 { > + compatible = "simple-bus"; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0x0 0xbb000000 0x10000>; > + }; > +}; > -- > 2.25.1 >
