Hi Samuel, Thanks a lot for working on this I'm fine with the rest of the work, but I have a couple of questions On Sun, Jan 03, 2021 at 04:30:52AM -0600, Samuel Holland wrote: > The R_INTC in the A31 and newer sun8i/sun50i SoCs has additional > functionality compared to the sun7i/sun9i NMI controller. Among other > things, it multiplexes up to 128 interrupts corresponding to (and in > parallel to) the first 128 GIC SPIs. This means the NMI is no longer the > lowest-numbered interrupt, since it is SPI 32 or 96 (depending on SoC). > > To allow access to all multiplexed IRQs, the R_INTC requires a new > binding where the interrupt number matches the GIC interrupt number. > For simplicity, copy the three-cell GIC binding; this disambiguates > interrupt 0 in the old binding (the NMI) from interrupt 0 in the new > binding (SPI 0) by the number of cells. It's not really clear to me what the ambiguity is between the NMI and the SPI 0 interrupt? In general, it looks like switching to a 3-cell binding with the GIC SPI value looks weird to me, since the GIC isn't the parent at all of these interrupts. If the ambiguity is that a stacked irqchip driver needs to have the same interrupt number than the GIC, and that the 0 interrupt for the NMI controller (used by the PMIC) and is actually the 32 (or 96) GIC interrupt and thus breaks that requirement, can't we fix this in the driver based on the compatible? Something like if the interrupt number is 0, with a A31 or newer compatible, then add the proper offset in sun6i_r_intc_domain_alloc? Maxime
