Add DT binding for phy_en_refclk used to route the refclk out of the
SERDES.
Signed-off-by: Kishon Vijay Abraham I <kishon@xxxxxx>
---
.../devicetree/bindings/phy/ti,phy-j721e-wiz.yaml | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml b/Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml
index 4a1f9c27b5f0..14823588bc94 100644
--- a/Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml
+++ b/Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml
@@ -149,6 +149,19 @@ patternProperties:
- assigned-clocks
- assigned-clock-parents
+ "^phy-en-refclk$":
+ type: object
+ description: |
+ In order to drive the refclk out from the SERDES (Cadence Torrent),
+ PHY_EN_REFCLK should be set in SERDES_RST of WIZ. Model phy-en-refclk
+ as a clock so that it can be enabled directly or as a parent clock.
+ properties:
+ "#clock-cells":
+ const: 0
+
+ required:
+ - "#clock-cells"
+
"^serdes@[0-9a-f]+$":
type: object
description: |
--
2.17.1
