Quoting Claudiu Beznea (2020-11-19 07:43:17) > Register CPU clock as being the master clock prescaler. This would > be used by DVFS. The block schema of SAMA7G5's PMC contains also a divider > between master clock prescaler and CPU (PMC_CPU_RATIO.RATIO) but the > frequencies supported by SAMA7G5 could be directly received from > CPUPLL + master clock prescaler and the extra divider would do no work in > case it would be enabled. > > Signed-off-by: Claudiu Beznea <claudiu.beznea@xxxxxxxxxxxxx> > --- Applied to clk-next
