On Tue, 22 Sep 2020 15:46:23 +0200
Lars-Peter Clausen <lars@xxxxxxxxxx> wrote:
> Add binding documentation for the Xilinx System Management Wizard. The
> Xilinx System Management Wizard is a AXI frontend for the Xilinx System
> Monitor found in the UltraScale and UltraScale+ FPGAs.
>
> The System Monitor is the equivalent to the Xilinx XADC found in their
> previous generation of FPGAs and their external and internal interfaces are
> very similar. For this reason the share the same binding documentation. But
> since they are not 100% compatible and software will have to know about the
> differences they use a different compatible string.
>
> Signed-off-by: Lars-Peter Clausen <lars@xxxxxxxxxx>
+CC relevant DT bindings people.
As this is fairly trivial I've fixed up the patch title to the usual
dt-bindings format and applied to the togreg branch of iio.git.
I don't want to delay this series even longer to go around again.
Thanks,
> ---
> .../bindings/iio/adc/xilinx-xadc.txt | 49 +++++++++++++++----
> 1 file changed, 39 insertions(+), 10 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/iio/adc/xilinx-xadc.txt b/Documentation/devicetree/bindings/iio/adc/xilinx-xadc.txt
> index e0e0755cabd8..f42e18078376 100644
> --- a/Documentation/devicetree/bindings/iio/adc/xilinx-xadc.txt
> +++ b/Documentation/devicetree/bindings/iio/adc/xilinx-xadc.txt
> @@ -1,13 +1,22 @@
> Xilinx XADC device driver
>
> -This binding document describes the bindings for both of them since the
> -bindings are very similar. The Xilinx XADC is a ADC that can be found in the
> -series 7 FPGAs from Xilinx. The XADC has a DRP interface for communication.
> -Currently two different frontends for the DRP interface exist. One that is only
> -available on the ZYNQ family as a hardmacro in the SoC portion of the ZYNQ. The
> -other one is available on all series 7 platforms and is a softmacro with a AXI
> -interface. This binding document describes the bindings for both of them since
> -the bindings are very similar.
> +This binding document describes the bindings for the Xilinx 7 Series XADC as well
> +as the UltraScale/UltraScale+ System Monitor.
> +
> +The Xilinx XADC is an ADC that can be found in the Series 7 FPGAs from Xilinx.
> +The XADC has a DRP interface for communication. Currently two different
> +frontends for the DRP interface exist. One that is only available on the ZYNQ
> +family as a hardmacro in the SoC portion of the ZYNQ. The other one is available
> +on all series 7 platforms and is a softmacro with a AXI interface. This binding
> +document describes the bindings for both of them since the bindings are very
> +similar.
> +
> +The Xilinx System Monitor is an ADC that is found in the UltraScale and
> +UltraScale+ FPGAs from Xilinx. The System Monitor provides a DRP interface for
> +communication. Xilinx provides a standard IP core that can be used to access the
> +System Monitor through an AXI interface in the FPGA fabric. This IP core is
> +called the Xilinx System Management Wizard. This document describes the bindings
> +for this IP.
>
> Required properties:
> - compatible: Should be one of
> @@ -15,11 +24,14 @@ Required properties:
> configuration interface to interface to the XADC hardmacro.
> * "xlnx,axi-xadc-1.00.a": When using the axi-xadc pcore to
> interface to the XADC hardmacro.
> + * "xlnx,system-management-wiz-1.3": When using the
> + Xilinx System Management Wizard fabric IP core to access the
> + UltraScale and UltraScale+ System Monitor.
> - reg: Address and length of the register set for the device
> - interrupts: Interrupt for the XADC control interface.
> - clocks: When using the ZYNQ this must be the ZYNQ PCAP clock,
> - when using the AXI-XADC pcore this must be the clock that provides the
> - clock to the AXI bus interface of the core.
> + when using the axi-xadc or the axi-system-management-wizard this must be
> + the clock that provides the clock to the AXI bus interface of the core.
>
> Optional properties:
> - xlnx,external-mux:
> @@ -110,3 +122,20 @@ Examples:
> };
> };
> };
> +
> + adc@80000000 {
> + compatible = "xlnx,system-management-wiz-1.3";
> + reg = <0x80000000 0x1000>;
> + interrupts = <0 81 4>;
> + interrupt-parent = <&gic>;
> + clocks = <&fpga1_clk>;
> +
> + xlnx,channels {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + channel@0 {
> + reg = <0>;
> + xlnx,bipolar;
> + };
> + };
> + };
