Cadence controller will not initiate autonomous speed change if strapped as Gen2. The Retrain Link bit is set as quirk to enable this speed change. Adding a quirk flag based on a new compatible string. In future IP revisions this will not be applicable. Version history: Changes in v4: - Added a quirk flag based on a new compatible string. - Change of api for link up: cdns_pcie_host_wait_for_link(). Changes in v3: - To set retrain link bit,checking device capability & link status. - 32bit read in place of 8bit. - Minor correction in patch comment. - Change in variable & macro name. Changes in v2: - 16bit read in place of 8bit. Nadeem Athani (2): dt-bindings: pci: Retrain Link to work around Gen2 training defect. PCI: cadence: Retrain Link to work around Gen2 training defect. .../bindings/pci/cdns,cdns-pcie-host.yaml | 4 +- drivers/pci/controller/cadence/pcie-cadence-host.c | 67 ++++++++++++++++------ drivers/pci/controller/cadence/pcie-cadence-plat.c | 13 +++++ drivers/pci/controller/cadence/pcie-cadence.h | 11 +++- 4 files changed, 76 insertions(+), 19 deletions(-) -- 2.15.0
