On Wed, 25 Nov 2020 11:32:00 +0100, Gregory CLEMENT wrote:
> Ocelot SoC belongs to a larger family of SoCs which use the same
> interrupt controller with a few variation.
>
> This series of patches add support for Luton, Serval and Jaguar2, they
> are all MIPS based.
>
> The first patches of the series also updates the binding documentation
> with the new compatible strings.
>
> [...]
Applied to irq/irqchip-next, thanks!
[1/6] dt-bindings: interrupt-controller: convert icpu intr bindings to json-schema
commit: 47d5e0b0e1c151c06885a78a108001ead96adc75
[2/6] dt-bindings: interrupt-controller: Add binding for few Microsemi interrupt controllers
commit: b307ee828f61bc65d918e820a93b5c547a73dda3
[3/6] irqchip: ocelot: prepare to support more SoC
commit: 5f0c75e7a1333f5ebb5303af55d8c863ea292c23
[4/6] irqchip: ocelot: Add support for Luton platforms
commit: ffce73d4415391b2d6da4878bf04d6610edf56db
[5/6] irqchip: ocelot: Add support for Serval platforms
commit: 7efdfbd15a21788de8c0743590e777f151a3031b
[6/6] irqchip: ocelot: Add support for Jaguar2 platforms
commit: 550c1424acf0123ba0c17e22dfcac92d152b2f0e
Cheers,
M.
--
Without deviation from the norm, progress is not possible.
