Hi all,
On Sun, Nov 22, 2020 at 10:55 AM Sergio Paracuellos
<sergio.paracuellos@xxxxxxxxx> wrote:
>
> This patchset ports CPU clock detection for MT7621 from OpenWrt
> and adds a complete clock plan for the mt7621 SOC.
>
> The documentation for this SOC only talks about two registers
> regarding to the clocks:
> * SYSC_REG_CPLL_CLKCFG0 - provides some information about boostrapped
> refclock. PLL and dividers used for CPU and some sort of BUS (AHB?).
> * SYSC_REG_CPLL_CLKCFG1 - a banch of gates to enable/disable clocks for
> all or some ip cores.
>
> No documentation about a probably existent set of dividers for each ip
> core is included in the datasheets. So we cannot make anything better,
> AFAICT.
>
> Looking into driver code, and some openWRT patched there are
> another frequences which are used in some drivers (uart, sd...).
> According to all of this information the clock plan for this
> SoC is set as follows:
> - Main top clock "xtal" from where all the rest of the world is
> derived.
> - CPU clock "cpu" derived from "xtal" frequencies and a bunch of
> register reads and predividers.
> - BUS clock "bus" derived from "cpu" and with (cpu / 4) MHz.
> - Fixed clocks from "xtal":
> * "50m": 50 MHz.
> * "125m": 125 MHz.
> * "150m": 150 MHz.
> * "250m": 250 MHz.
> * "270m": 270 MHz.
>
> We also have a buch of gate clocks with their parents:
> - "hsdma": "150m"
> - "fe": "250m"
> - "sp_divtx": "270m"
> - "timer": "50m"
> - "pcm": "270m"
> - "pio": "50m"
> - "gdma": "bus"
> - "nand": "125m"
> - "i2c": "50m"
> - "i2s": "270m"
> - "spi": "bus"
> - "uart1": "50m"
> - "uart2": "50m"
> - "uart3": "50m"
> - "eth": "50m"
> - "pcie0": "125m"
> - "pcie1": "125m"
> - "pcie2": "125m"
> - "crypto": "250m"
> - "shxc": "50m"
>
> There was a previous attempt of doing this here[0] but the author
> (Chuanhong Guo) did not wanted to make assumptions of a clock plan
> for the platform that time. It seems that now he has a better idea of
> how the clocks are dispossed for this SoC so he share code[1] where
> some frequencies and clock parents for the gates are coded from a
> real mediatek private clock plan.
>
> I do really want this to be upstreamed so according to the comments
> in previous attempt[0] from Oleksij Rempel and the frequencies in
> code[1] I have tried to do this by myself.
>
> All of this patches have been tested in a GNUBee PC1 resulting in a
> working platform.
>
> Changes in v4:
> - Add Acked-by from Rob Herring for binding headers (PATCH 1/6).
> - Convert bindings to not use syscon phandle and declare clock as
> a child of the syscon node. Update device tree and binding doc
> accordly.
> - Make use of 'syscon_node_to_regmap' in driver code instead of
> get this using the phandle function.
> - Properly unregister clocks for the error path of the function
> 'mt7621_clk_init'.
> - Include ARRAY_SIZE of fixed clocks in the 'count' to kzalloc
> of 'clk_data'.
> - Add new patch changing invalid vendor 'mtk' in favour of 'mediatek'
> which is the one listed in 'vendor-prefixes.yaml'. Update mt7621 code
> accordly. I have added this patch inside this series because clk
> binding is referring syscon node and the string for that node was
> with not listed vendor. Hence update and have all of this correct
> in the same series.
Any comments on this?? Should I resend the series to get reviewed?
Thanks in advance for your time!
Best regards,
Sergio Paracuellos
>
> Changes in v3:
> - Fix compilation warnings reported by kernel test robot because of
> ignoring return values of 'of_clk_hw_register' in functions
> 'mt7621_register_top_clocks' and 'mt7621_gate_ops_init'.
> - Fix dts file and binding documentation 'clock-output-names'.
>
> Changes in v2:
> - Remove the following patches:
> * dt: bindings: add mt7621-pll device tree binding documentation.
> * MIPS: ralink: add clock device providing cpu/ahb/apb clock for mt7621.
> - Move all relevant clock code to 'drivers/clk/ralink/clk-mt7621.c' and
> unify there previous 'mt7621-pll' and 'mt7621-clk' into a unique driver
> and binding 'mt7621-clk'.
> - Driver is not a platform driver anymore and now make use of 'CLK_OF_DECLARE'
> because we need clocks available in 'plat_time_init' before setting up
> the timer for the GIC.
> - Use new fixed clocks as parents for different gates and deriving from 'xtal'
> using frequencies in[1].
> - Adapt dts file and bindings header and documentation for new changes.
> - Change MAINTAINERS file to only contains clk-mt7621.c code and
> mediatek,mt7621-clk.yaml file.
>
> [0]: https://www.lkml.org/lkml/2019/7/23/1044
> [1]: https://github.com/981213/linux/commit/2eca1f045e4c3db18c941135464c0d7422ad8133
>
>
> Sergio Paracuellos (6):
> dt-bindings: clock: add dt binding header for mt7621 clocks
> dt: bindings: add mt7621-clk device tree binding documentation
> clk: ralink: add clock driver for mt7621 SoC
> staging: mt7621-dts: make use of new 'mt7621-clk'
> staging: mt7621-dts: use valid vendor 'mediatek' instead of invalid
> 'mtk'
> MAINTAINERS: add MT7621 CLOCK maintainer
>
> .../bindings/clock/mediatek,mt7621-clk.yaml | 67 +++
> MAINTAINERS | 6 +
> arch/mips/ralink/mt7621.c | 6 +-
> drivers/clk/Kconfig | 1 +
> drivers/clk/Makefile | 1 +
> drivers/clk/ralink/Kconfig | 14 +
> drivers/clk/ralink/Makefile | 2 +
> drivers/clk/ralink/clk-mt7621.c | 434 ++++++++++++++++++
> drivers/staging/mt7621-dts/gbpc1.dts | 11 -
> drivers/staging/mt7621-dts/mt7621.dtsi | 85 ++--
> include/dt-bindings/clock/mt7621-clk.h | 41 ++
> 11 files changed, 609 insertions(+), 59 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/clock/mediatek,mt7621-clk.yaml
> create mode 100644 drivers/clk/ralink/Kconfig
> create mode 100644 drivers/clk/ralink/Makefile
> create mode 100644 drivers/clk/ralink/clk-mt7621.c
> create mode 100644 include/dt-bindings/clock/mt7621-clk.h
>
> --
> 2.25.1
>
