Hi Laurent,
On Tue, 2020-12-08 at 14:38 +0200, Laurent Pinchart wrote:
> Hi Liu,
>
> Thank you for the patch.
>
> On Fri, Dec 04, 2020 at 03:33:42PM +0800, Liu Ying wrote:
> > This patch allows LVDS PHYs to be configured through
> > the generic functions and through a custom structure
> > added to the generic union.
> >
> > The parameters added here are based on common LVDS PHY
> > implementation practices. The set of parameters
> > should cover all potential users.
> >
> > Cc: Kishon Vijay Abraham I <kishon@xxxxxx>
> > Cc: Vinod Koul <vkoul@xxxxxxxxxx>
> > Cc: NXP Linux Team <linux-imx@xxxxxxx>
> > Signed-off-by: Liu Ying <victor.liu@xxxxxxx>
> > ---
> > include/linux/phy/phy-lvds.h | 48 ++++++++++++++++++++++++++++++++++++++++++++
> > include/linux/phy/phy.h | 4 ++++
> > 2 files changed, 52 insertions(+)
> > create mode 100644 include/linux/phy/phy-lvds.h
> >
> > diff --git a/include/linux/phy/phy-lvds.h b/include/linux/phy/phy-lvds.h
> > new file mode 100644
> > index 00000000..1b5b9d6
> > --- /dev/null
> > +++ b/include/linux/phy/phy-lvds.h
> > @@ -0,0 +1,48 @@
> > +/* SPDX-License-Identifier: GPL-2.0 */
> > +/*
> > + * Copyright 2020 NXP
> > + */
> > +
> > +#ifndef __PHY_LVDS_H_
> > +#define __PHY_LVDS_H_
> > +
> > +/**
> > + * struct phy_configure_opts_lvds - LVDS configuration set
> > + *
> > + * This structure is used to represent the configuration state of a
> > + * LVDS phy.
> > + */
> > +struct phy_configure_opts_lvds {
> > + /**
> > + * @bits_per_lane_and_dclk_cycle:
> > + *
> > + * Number of bits per data lane and differential clock cycle.
> > + */
> > + unsigned int bits_per_lane_and_dclk_cycle;
>
> I see in patch 4/4 that you only support 7, can the value be any
> different ?
Patch 4/4 is for the Mixel combo PHY embedded in i.MX8qxp SoC.
This PHY can only do 7.
i.MX8qm SoC embeds another type of Mixel LVDS PHY which can do either 7
or 10(configurable with a register bit called 'NB'). A PHY driver for
it is yet to be upstreamed.
Regards,
Liu Ying
>
> > +
> > + /**
> > + * @differential_clk_rate:
> > + *
> > + * Clock rate, in Hertz, of the LVDS differential clock.
> > + */
> > + unsigned long differential_clk_rate;
> > +
> > + /**
> > + * @lanes:
> > + *
> > + * Number of active, consecutive, data lanes, starting from
> > + * lane 0, used for the transmissions.
> > + */
> > + unsigned int lanes;
> > +
> > + /**
> > + * @is_slave:
> > + *
> > + * Boolean, true if the phy is a slave which works together
> > + * with a master phy to support dual link transmission,
> > + * otherwise a regular phy or a master phy.
> > + */
> > + bool is_slave;
> > +};
> > +
> > +#endif /* __PHY_LVDS_H_ */
> > diff --git a/include/linux/phy/phy.h b/include/linux/phy/phy.h
> > index e435bdb..d450b44 100644
> > --- a/include/linux/phy/phy.h
> > +++ b/include/linux/phy/phy.h
> > @@ -17,6 +17,7 @@
> > #include <linux/regulator/consumer.h>
> >
> > #include <linux/phy/phy-dp.h>
> > +#include <linux/phy/phy-lvds.h>
> > #include <linux/phy/phy-mipi-dphy.h>
> >
> > struct phy;
> > @@ -51,10 +52,13 @@ enum phy_mode {
> > * the MIPI_DPHY phy mode.
> > * @dp: Configuration set applicable for phys supporting
> > * the DisplayPort protocol.
> > + * @lvds: Configuration set applicable for phys supporting
> > + * the LVDS phy mode.
> > */
> > union phy_configure_opts {
> > struct phy_configure_opts_mipi_dphy mipi_dphy;
> > struct phy_configure_opts_dp dp;
> > + struct phy_configure_opts_lvds lvds;
> > };
> >
> > /**
