On Tue, Dec 01, 2020 at 02:34:51PM -0800, mgross@xxxxxxxxxxxxxxx wrote: > From: Daniele Alessandrelli <daniele.alessandrelli@xxxxxxxxx> > > Add DT binding documentation for the Intel Keem Bay IPC driver, which > enables communication between the Computing Sub-System (CSS) and the > Multimedia Sub-System (MSS) of the Intel Movidius SoC code named Keem > Bay. > > Cc: devicetree@xxxxxxxxxxxxxxx > Reviewed-by: Mark Gross <mgross@xxxxxxxxxxxxxxx> > Signed-off-by: Daniele Alessandrelli <daniele.alessandrelli@xxxxxxxxx> > --- > .../bindings/soc/intel/intel,keembay-ipc.yaml | 63 +++++++++++++++++++ > 1 file changed, 63 insertions(+) > create mode 100644 Documentation/devicetree/bindings/soc/intel/intel,keembay-ipc.yaml > > diff --git a/Documentation/devicetree/bindings/soc/intel/intel,keembay-ipc.yaml b/Documentation/devicetree/bindings/soc/intel/intel,keembay-ipc.yaml > new file mode 100644 > index 000000000000..6e21c54d8f34 > --- /dev/null > +++ b/Documentation/devicetree/bindings/soc/intel/intel,keembay-ipc.yaml > @@ -0,0 +1,63 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +# Copyright (C) 2020 Intel Corporation > +%YAML 1.2 > +--- > +$id: "http://devicetree.org/schemas/soc/intel/intel,keembay-ipc.yaml#"; > +$schema: "http://devicetree.org/meta-schemas/core.yaml#"; > + > +title: Keem Bay IPC > + > +maintainers: > + - Daniele Alessandrelli <daniele.alessandrelli@xxxxxxxxx> > + > +description: > + The Keem Bay IPC driver enables Inter-Processor Communication (IPC) with the > + Visual Processor Unit (VPU) embedded in the Intel Movidius SoC code named > + Keem Bay. Sounds like a mailbox. What's the relationship between this and the xlink thing? > + > +properties: > + compatible: > + const: intel,keembay-ipc > + > + reg: > + items: > + - description: The CSS (CPU) FIFO registers > + - description: The MSS (VPU) FIFO registers > + > + reg-names: > + items: > + - const: css_fifo > + - const: mss_fifo > + > + interrupts: > + items: > + - description: CSS FIFO not-empty interrupt > + > + interrupt-controller: true > + > + memory-region: > + items: > + - description: Reserved memory region used for CSS IPC buffers > + - description: Reserved memory region used for MSS IPC buffers > + > +required: > + - compatible > + - reg > + - reg-names > + - interrupts > + - memory-region > + > +additionalProperties: false > + > +examples: > + - | > + #include <dt-bindings/interrupt-controller/irq.h> > + #include <dt-bindings/interrupt-controller/arm-gic.h> > + ipc@203300f0 { > + compatible = "intel,keembay-ipc"; > + reg = <0x203300f0 0x310>, /* CPU TIM FIFO */ > + <0x208200f0 0x310>; /* VPU TIM FIFO */ > + reg-names = "css_fifo", "mss_fifo"; > + interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; > + memory-region = <&css_ipc_reserved>, <&mss_ipc_reserved>; > + }; > -- > 2.17.1 >
