[PATCH] arm64: dts imx8mm: Add power domains

[Adrien Grassein <adrien.grassein@xxxxxxxxx>]

Power domains were not defined for imx8mm
but, according to spec, they are the same as on
the imx8mq SoC.

Tested on a Boundary Nitrogen 8M Mini board.


Signed-off-by: Adrien Grassein <adrien.grassein@xxxxxxxxx>
---
 arch/arm64/boot/dts/freescale/imx8mm.dtsi | 76 +++++++++++++++++++++++
 1 file changed, 76 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
index 05ee062548e4..72f69a6da5c3 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
@@ -8,6 +8,7 @@
 #include <dt-bindings/input/input.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/thermal/thermal.h>
+#include <dt-bindings/power/imx8mq-power.h>
 
 #include "imx8mm-pinfunc.h"
 
@@ -549,6 +550,81 @@
 			};
 		};
 
+		gpc: gpc@303a0000 {
+			compatible = "fsl,imx8mq-gpc";
+			reg = <0x303a0000 0x10000>;
+			interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-parent = <&gic>;
+			interrupt-controller;
+			#interrupt-cells = <3>;
+
+			pgc {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				pgc_mipi: power-domain@0 {
+					#power-domain-cells = <0>;
+					reg = <IMX8M_POWER_DOMAIN_MIPI>;
+				};
+
+				/*
+				 * As per comment in ATF source code:
+				 *
+				 * PCIE1 and PCIE2 share the
+				 * same reset signal, if we
+				 * power down PCIE2, PCIE1
+				 * will be held in reset too.
+				 *
+				 * So instead of creating two
+				 * separate power domains for
+				 * PCIE1 and PCIE2 we create a
+				 * link between both and use
+				 * it as a shared PCIE power
+				 * domain.
+				 */
+				pgc_pcie: power-domain@1 {
+					#power-domain-cells = <0>;
+					reg = <IMX8M_POWER_DOMAIN_PCIE1>;
+					power-domains = <&pgc_pcie2>;
+				};
+
+				pgc_otg1: power-domain@2 {
+					#power-domain-cells = <0>;
+					reg = <IMX8M_POWER_DOMAIN_USB_OTG1>;
+				};
+
+				pgc_otg2: power-domain@3 {
+					#power-domain-cells = <0>;
+					reg = <IMX8M_POWER_DOMAIN_USB_OTG2>;
+				};
+
+				pgc_ddr1: power-domain@4 {
+					#power-domain-cells = <0>;
+					reg = <IMX8M_POWER_DOMAIN_DDR1>;
+				};
+
+				pgc_disp: power-domain@7 {
+					#power-domain-cells = <0>;
+					reg = <IMX8M_POWER_DOMAIN_DISP>;
+				};
+
+				pgc_mipi_csi1: power-domain@8 {
+					#power-domain-cells = <0>;
+					reg = <IMX8M_POWER_DOMAIN_MIPI_CSI1>;
+				};
+
+				pgc_mipi_csi2: power-domain@9 {
+					#power-domain-cells = <0>;
+					reg = <IMX8M_POWER_DOMAIN_MIPI_CSI2>;
+				};
+
+				pgc_pcie2: power-domain@a {
+					#power-domain-cells = <0>;
+					reg = <IMX8M_POWER_DOMAIN_PCIE2>;
+				};
+			};
+		};
+
 		aips2: bus@30400000 {
 			compatible = "fsl,aips-bus", "simple-bus";
 			reg = <0x30400000 0x400000>;
-- 
2.20.1