On 6/24/2014 11:11 AM, Will Deacon wrote:
> On Tue, Jun 24, 2014 at 06:57:44PM +0100, Olav Haugan wrote:
>> On 6/24/2014 2:18 AM, Will Deacon wrote:
>>> On Sat, Jun 21, 2014 at 12:16:25AM +0100, Olav Haugan wrote:
>>>> We have multiple-master SMMUs and each master emits a variable number of
>>>> StreamIDs. However, we have to apply a mask (the ARM SMMU spec allows
>>>> for this) to the StreamIDs due to limited number of StreamID 2 Context
>>>> Bank entries in the SMMU. If my understanding is correct we would
>>>> represent this in the DT like this:
>>>>
>>>> iommu {
>>>> #address-cells = <2>;
>>>> #size-cells = <0>;
>>>> };
>>>>
>>>> master@a {
>>>> ...
>>>> iommus = <&iommu StreamID0 MASK0>,
>>>> <&iommu StreamID1 MASK1>,
>>>> <&iommu StreamID2 MASK2>;
>>>> };
>>>
>>> Stupid question, but why not simply describe the masked IDs? What use does
>>> the `raw' ID have to Linux?
>>
>> We do describe the masked StreamID (SID) but we need to specify the mask
>> that the SMMU should apply to the incoming SIDs, right?
>>
>> We have a bus master that emits 43 unique SIDs. However, we have only 40
>> SMMU_SMRn registers in the SMMU. So we need to mask out some of the
>> incoming SID bits so that the 43 SIDs can match one of 40 entries in the
>> SMR.
>
> Hmm, so you're talking about stream matching, right? That doesn't belong in
> the device-tree. I appreciate that the current driver does a terrible job at
> allocating the SMRs (it's bloody difficult!), but we should try to improve
> the dynamic behaviour instead of moving configuration of the SMMU out into
> device-tree, where it's inflexible at best.
I am talking about SMMU_SMRn[MASK] register bits. This is not something
that can be dynamically detected at run-time. It is configuration at the
same level as the actual StreamIDs.
Thanks,
Olav Haugan
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