From: Vijayakannan Ayyathurai <vijayakannan.ayyathurai@xxxxxxxxx> Add Device Tree bindings for the Timer IP, which used as clocksource and clockevent in the Intel Keem Bay SoC. Signed-off-by: Vijayakannan Ayyathurai <vijayakannan.ayyathurai@xxxxxxxxx> Acked-by: Mark Gross <mgross@xxxxxxxxxxxxxxx> Acked-by: Andy Shevchenko <andriy.shevchenko@xxxxxxxxxxxxxxx> --- .../bindings/timer/intel,keembay-timer.yaml | 72 +++++++++++++++++++ 1 file changed, 72 insertions(+) create mode 100644 Documentation/devicetree/bindings/timer/intel,keembay-timer.yaml diff --git a/Documentation/devicetree/bindings/timer/intel,keembay-timer.yaml b/Documentation/devicetree/bindings/timer/intel,keembay-timer.yaml new file mode 100644 index 000000000000..396a698967ca --- /dev/null +++ b/Documentation/devicetree/bindings/timer/intel,keembay-timer.yaml @@ -0,0 +1,72 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/timer/intel,keembay-timer.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Intel Keem Bay SoC Timers + +maintainers: + - Wan Ahmad Zainie <wan.ahmad.zainie.wan.mohamad@xxxxxxxxx> + +description: + Intel Keem Bay SoC Timers block contains 8 32-bit general purpose timers, + a free running 64-bit counter, a random number generator and a watchdog + timer. Each gpt can generate an individual interrupt. + +properties: + compatible: + oneOf: + - items: + enum: + - intel,keembay-timer + - intel,keembay-counter + + reg: + maxItems: 2 + + clocks: + maxItems: 1 + + interrupts: + maxItems: 1 + +required: + - compatible + - reg + - clocks + +allOf: + - if: + properties: + compatible: + contains: + enum: + - intel,keembay-timer + then: + properties: + interrupts: + maxItems: 1 + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/interrupt-controller/irq.h> + #define KEEM_BAY_A53_TIM + + timer@20330010 { + compatible = "intel,keembay-timer"; + reg = <0x20330010 0xc>, + <0x20331000 0xc>; + interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&scmi_clk KEEM_BAY_A53_TIM>; + }; + + counter@203300e8 { + compatible = "intel,keembay-counter"; + reg = <0x203300e8 0xc>, + <0x20331000 0xc>; + clocks = <&scmi_clk KEEM_BAY_A53_TIM>; + }; -- 2.17.1
