On Wed, Nov 25, 2020 at 06:11:52PM +0800, Wan Ahmad Zainie wrote:
> Add driver for Intel Keem Bay SoC PCIe controller. This controller
> is based on DesignWare PCIe core.
>
> In root complex mode, only internal reference clock is possible for
> Keem Bay A0. For Keem Bay B0, external reference clock can be used
> and will be the default configuration. Currently, keembay_pcie_of_data
> structure has one member. It will be expanded later to handle this
> difference.
>
> Endpoint mode link initialization is handled by the boot firmware.
...
> + switch (pcie->mode) {
> + case DW_PCIE_RC_TYPE:
> + if (!IS_ENABLED(CONFIG_PCIE_KEEMBAY_HOST))
> + return -ENODEV;
> +
> + ret = keembay_pcie_add_pcie_port(pcie, pdev);
> + if (ret < 0)
> + return ret;
> + break;
return keembay_pcie_add_pcie_port(pcie, pdev);
> + case DW_PCIE_EP_TYPE:
> + if (!IS_ENABLED(CONFIG_PCIE_KEEMBAY_EP))
> + return -ENODEV;
> +
> + pci->ep.ops = &keembay_pcie_ep_ops;
> + return dw_pcie_ep_init(&pci->ep);
> + default:
> + dev_err(dev, "Invalid device type %d\n", pcie->mode);
> + return -ENODEV;
> + }
> + return 0;
...and drop this one.
> +}
--
With Best Regards,
Andy Shevchenko
