On 20/11/2020 10:58, Vinod Koul wrote: > On 16-11-20, 11:16, Neil Armstrong wrote: >> The AXG Analog MIPI-DSI PHY also provides functions to the PCIe PHY, >> thus we need to have inclusive support for both interfaces at runtime. >> >> This fixes the regmap get from parent node, removes cell param >> to select a mode and implement runtime configuration & power on/off >> for both functions since they are not exclusive. >> >> Signed-off-by: Neil Armstrong <narmstrong@xxxxxxxxxxxx> >> Reviewed-by: Remi Pommarel <repk@xxxxxxxxxxxx> >> --- >> drivers/phy/amlogic/Kconfig | 1 + >> .../amlogic/phy-meson-axg-mipi-pcie-analog.c | 204 ++++++++++++------ >> 2 files changed, 136 insertions(+), 69 deletions(-) >> >> diff --git a/drivers/phy/amlogic/Kconfig b/drivers/phy/amlogic/Kconfig >> index 99e8a4c7f1f3..db5d0cd757e3 100644 >> --- a/drivers/phy/amlogic/Kconfig >> +++ b/drivers/phy/amlogic/Kconfig >> @@ -66,6 +66,7 @@ config PHY_MESON_AXG_MIPI_PCIE_ANALOG >> depends on OF && (ARCH_MESON || COMPILE_TEST) >> select GENERIC_PHY >> select REGMAP_MMIO >> + select GENERIC_PHY_MIPI_DPHY >> help >> Enable this to support the Meson MIPI + PCIE analog PHY >> found in Meson AXG SoCs. >> diff --git a/drivers/phy/amlogic/phy-meson-axg-mipi-pcie-analog.c b/drivers/phy/amlogic/phy-meson-axg-mipi-pcie-analog.c >> index 1431cbf885e1..6eb21551bdd9 100644 >> --- a/drivers/phy/amlogic/phy-meson-axg-mipi-pcie-analog.c >> +++ b/drivers/phy/amlogic/phy-meson-axg-mipi-pcie-analog.c >> @@ -4,9 +4,13 @@ >> * >> * Copyright (C) 2019 Remi Pommarel <repk@xxxxxxxxxxxx> >> */ >> +#include <linux/bitfield.h> >> +#include <linux/bitops.h> >> #include <linux/module.h> >> #include <linux/phy/phy.h> >> #include <linux/regmap.h> >> +#include <linux/delay.h> >> +#include <linux/mfd/syscon.h> >> #include <linux/platform_device.h> >> #include <dt-bindings/phy/phy.h> >> >> @@ -14,10 +18,10 @@ >> #define HHI_MIPI_CNTL0_COMMON_BLOCK GENMASK(31, 28) >> #define HHI_MIPI_CNTL0_ENABLE BIT(29) >> #define HHI_MIPI_CNTL0_BANDGAP BIT(26) >> -#define HHI_MIPI_CNTL0_DECODE_TO_RTERM GENMASK(15, 12) >> -#define HHI_MIPI_CNTL0_OUTPUT_EN BIT(3) >> +#define HHI_MIPI_CNTL0_DIF_REF_CTL1 GENMASK(25, 16) >> +#define HHI_MIPI_CNTL0_DIF_REF_CTL0 GENMASK(15, 0) >> >> -#define HHI_MIPI_CNTL1 0x01 >> +#define HHI_MIPI_CNTL1 0x04 >> #define HHI_MIPI_CNTL1_CH0_CML_PDR_EN BIT(12) >> #define HHI_MIPI_CNTL1_LP_ABILITY GENMASK(5, 4) >> #define HHI_MIPI_CNTL1_LP_RESISTER BIT(3) >> @@ -25,100 +29,170 @@ >> #define HHI_MIPI_CNTL1_INPUT_SEL BIT(1) >> #define HHI_MIPI_CNTL1_PRBS7_EN BIT(0) >> >> -#define HHI_MIPI_CNTL2 0x02 >> +#define HHI_MIPI_CNTL2 0x08 >> #define HHI_MIPI_CNTL2_CH_PU GENMASK(31, 25) >> #define HHI_MIPI_CNTL2_CH_CTL GENMASK(24, 19) >> #define HHI_MIPI_CNTL2_CH0_DIGDR_EN BIT(18) >> #define HHI_MIPI_CNTL2_CH_DIGDR_EN BIT(17) >> #define HHI_MIPI_CNTL2_LPULPS_EN BIT(16) >> -#define HHI_MIPI_CNTL2_CH_EN(n) BIT(15 - (n)) >> +#define HHI_MIPI_CNTL2_CH_EN GENMASK(15, 11) >> #define HHI_MIPI_CNTL2_CH0_LP_CTL GENMASK(10, 1) >> >> +#define DSI_LANE_0 (1 << 4) >> +#define DSI_LANE_1 (1 << 3) >> +#define DSI_LANE_CLK (1 << 2) >> +#define DSI_LANE_2 (1 << 1) >> +#define DSI_LANE_3 (1 << 0) >> +#define DSI_LANE_MASK (0x1F) > > This should use BIT(), also there are interesting helpers in bitfield.h > to help with register fields, do send follow up patches.. > Ok, cleanup will follow Thanks, Neil
