Hello, On 16/11/2020 17:24:24+0100, Gregory CLEMENT wrote: > Add the Device Tree binding documentation for the Microsemi Jaguar2, > Luton and Serval interrupt controller that is part of the ICPU. It is > connected directly to the MIPS core interrupt controller. > > Signed-off-by: Gregory CLEMENT <gregory.clement@xxxxxxxxxxx> > --- > .../bindings/interrupt-controller/mscc,ocelot-icpu-intr.yaml | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.yaml b/Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.yaml > index 3a537635a859..5483ed7062ba 100644 > --- a/Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.yaml > +++ b/Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.yaml > @@ -21,7 +21,11 @@ properties: > compatible: > items: > - enum: > + - mscc,jaguar2-icpu-intr > + - mscc,luton-icpu-intr > - mscc,ocelot-icpu-intr > + - mscc,serval-icpu-intr > + Spurious blank line > > '#interrupt-cells': > const: 1 > -- > 2.29.2 > -- Alexandre Belloni, Bootlin Embedded Linux and Kernel engineering https://bootlin.com
