The Hiedma Controller v310 Provides eight DMA channels, each channel can be configured for one-way transfer. The data can be transferred in 8-bit, 16-bit, 32-bit, or 64-bit mode. This documentation describes DT bindings of this controller. Signed-off-by: Dongjiu Geng <gengdongjiu@xxxxxxxxxx> --- .../bindings/dma/hisilicon,hiedmacv310.yaml | 80 +++++++++++++++++++ 1 file changed, 80 insertions(+) create mode 100644 Documentation/devicetree/bindings/dma/hisilicon,hiedmacv310.yaml diff --git a/Documentation/devicetree/bindings/dma/hisilicon,hiedmacv310.yaml b/Documentation/devicetree/bindings/dma/hisilicon,hiedmacv310.yaml new file mode 100644 index 000000000000..c04603316b40 --- /dev/null +++ b/Documentation/devicetree/bindings/dma/hisilicon,hiedmacv310.yaml @@ -0,0 +1,80 @@ +# SPDX-License-Identifier: GPL-2.0-only +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/dma/hisilicon,hiedmacv310.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: HiSilicon Hiedma Controller v310 Device Tree Bindings + +description: | + These bindings describe the DMA engine included in the HiSilicon Hiedma + Controller v310 Device. + +maintainers: + - Dongjiu Geng <gengdongjiu@xxxxxxxxxx> + +allOf: + - $ref: "dma-controller.yaml#" + +properties: + "#dma-cells": + const: 2 + + compatible: + const: hisilicon,hiedmacv310_n + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + items: + - description: apb clock + - description: axi clock + + clock-names: + items: + - const: apb_pclk + - const: axi_aclk + +required: + - "#dma-cells" + - "#clock-cells" + - compatible + - reg + - interrupts + - clocks + - clock-names + - resets + - reset-names + - dma-requests + - dma-channels + - devid + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/clock/hi3559av100-clock.h> + + dma: dma-controller@10040000 { + compatible = "hisilicon,hiedmacv310_n"; + reg = <0x10040000 0x1000>; + misc_regmap = <&misc_ctrl>; + misc_ctrl_base = <0x144>; + interrupts = <0 82 4>; + clocks = <&clock HI3559AV100_EDMAC1_CLK>, <&clock HI3559AV100_EDMAC1_AXICLK>; + clock-names = "apb_pclk", "axi_aclk"; + #clock-cells = <2>; + resets = <&clock 0x16c 7>; + reset-names = "dma-reset"; + dma-requests = <32>; + dma-channels = <8>; + devid = <1>; + #dma-cells = <2>; + }; + +... -- 2.17.1
