On 00:41-20201103, Faiz Abbas wrote:
> There are 4 instances of gpio modules in main domain:
> gpio0, gpio2, gpio4 and gpio6
>
> Groups are created to provide protection between different processor virtual
> worlds. Each of these modules I/O pins are muxed within the group. Exactly
> one module can be selected to control the corresponding pin by selecting it
> in the pad mux configuration registers.
Could you check with checkpatch --strict please?
I see:
WARNING: Possible unwrapped commit description (prefer a maximum 75 chars per line)
>
> This group pins out 69 lines (5 banks).
>
> Add DT modes for each module instance in the main domain.
>
> Signed-off-by: Faiz Abbas <faiz_abbas@xxxxxx>
> ---
> arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 68 +++++++++++++++++++++++
dtbs_check: we added:
arch/arm64/boot/dts/ti/k3-j7200-main.dtsi: /bus@100000/gpio@600000: Missing #address-cells in interrupt provider
arch/arm64/boot/dts/ti/k3-j7200-main.dtsi: /bus@100000/gpio@610000: Missing #address-cells in interrupt provider
arch/arm64/boot/dts/ti/k3-j7200-main.dtsi: /bus@100000/gpio@620000: Missing #address-cells in interrupt provider
arch/arm64/boot/dts/ti/k3-j7200-main.dtsi: /bus@100000/gpio@630000: Missing #address-cells in interrupt provider
> 1 file changed, 68 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
> index 72d6496e88dd..c22ef2efa531 100644
> --- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
> @@ -446,4 +446,72 @@
> dr_mode = "otg";
> };
> };
> +
> + main_gpio0: gpio@600000 {
> + compatible = "ti,j721e-gpio", "ti,keystone-gpio";
> + reg = <0x00 0x00600000 0x00 0x100>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-parent = <&main_gpio_intr>;
> + interrupts = <145>, <146>, <147>, <148>,
> + <149>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + ti,ngpio = <69>;
> + ti,davinci-gpio-unbanked = <0>;
> + power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>;
> + clocks = <&k3_clks 105 0>;
> + clock-names = "gpio";
> + };
> +
> + main_gpio2: gpio@610000 {
> + compatible = "ti,j721e-gpio", "ti,keystone-gpio";
> + reg = <0x00 0x00610000 0x00 0x100>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-parent = <&main_gpio_intr>;
> + interrupts = <154>, <155>, <156>, <157>,
> + <158>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + ti,ngpio = <69>;
> + ti,davinci-gpio-unbanked = <0>;
> + power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>;
> + clocks = <&k3_clks 107 0>;
> + clock-names = "gpio";
> + };
> +
> + main_gpio4: gpio@620000 {
> + compatible = "ti,j721e-gpio", "ti,keystone-gpio";
> + reg = <0x00 0x00620000 0x00 0x100>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-parent = <&main_gpio_intr>;
> + interrupts = <163>, <164>, <165>, <166>,
> + <167>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + ti,ngpio = <69>;
> + ti,davinci-gpio-unbanked = <0>;
> + power-domains = <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>;
> + clocks = <&k3_clks 109 0>;
> + clock-names = "gpio";
> + };
> +
> + main_gpio6: gpio@630000 {
> + compatible = "ti,j721e-gpio", "ti,keystone-gpio";
> + reg = <0x00 0x00630000 0x00 0x100>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-parent = <&main_gpio_intr>;
> + interrupts = <172>, <173>, <174>, <175>,
> + <176>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + ti,ngpio = <69>;
> + ti,davinci-gpio-unbanked = <0>;
> + power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>;
> + clocks = <&k3_clks 111 0>;
> + clock-names = "gpio";
> + };
> };
> --
> 2.17.1
>
>
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>
--
Regards,
Nishanth Menon
Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3 1A34 DDB5 849D 1736 249D
