Hello,
Ocelot SoC belongs to a larger family of SoCs which use the same
interrupt controller with a few variation.
This series of patches add support for Luton, Serval and Jaguar2, they
are all MIPS based.
The first patches of the series also updates the binding documentation
with the new compatible strings.
Gregory
Changelog:
v1 -> v2:
- Convert the binding to yaml
- Squashed the patches adding new binding in a single one
Gregory CLEMENT (5):
dt-bindings: interrupt-controller: convert icpu intr bindings to
json-schema
dt-bindings: interrupt-controller: Add binding for few Microsemi
interrupt controllers
irqchip: ocelot: Add support for Luton platforms
irqchip: ocelot: Add support for Serval platforms
irqchip: ocelot: Add support for Jaguar2 platforms
.../mscc,ocelot-icpu-intr.txt | 21 --
.../mscc,ocelot-icpu-intr.yaml | 63 ++++++
drivers/irqchip/irq-mscc-ocelot.c | 183 ++++++++++++++++--
3 files changed, 225 insertions(+), 42 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.txt
create mode 100644 Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.yaml
--
2.28.0
