On Sat, Jun 21, 2014 at 12:00:36AM +0200, Beniamino Galvani wrote:
> On Tue, Jun 17, 2014 at 11:42:58PM +0200, Thierry Reding wrote:
> > On Thu, May 08, 2014 at 01:08:33AM +0200, Beniamino Galvani wrote:
[...]
> > > diff --git a/drivers/pwm/pwm-rockchip.c b/drivers/pwm/pwm-rockchip.c
[...]
> > > +static int rockchip_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
> > > + int duty_ns, int period_ns)
> > > +{
> > > + struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip);
> > > + unsigned long clk_rate, period, duty;
> > > + u64 div;
> > > + int ret;
> > > +
> > > + clk_rate = clk_get_rate(pc->clk);
> > > +
> > > + /*
> > > + * Since period and duty cycle registers have a width of 32
> > > + * bits, every possible input period can be obtained using the
> > > + * default prescaler value for all practical clock rate values.
> > > + */
> > > + div = clk_rate;
> > > + div *= period_ns;
> >
> > Perhaps shorten this to "div = clk_rate * period_ns;"?
>
> I will change this, adding a cast to avoid the truncation of the
> result to 32 bits: "div = (u64)clk_rate * period_ns;"
Alternatively you could simply make clk_rate a u64 since it's only used
in this context anyway.
Thierry
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