On Layerscape SoCs which feature the FlexSPI controller there is a single register which can control the divider value. The base frequency is the platform PLL. Right now the LS1028A and the LX2160A aren't able to switch the SCK frequency on the FlexSPI interface. Add a new clock driver which operate on said register. Michael Walle (5): clk: divider: add devm_clk_hw_register_divider_table() dt-bindings: clock: document the fsl-flexspi-clk driver clk: fsl-flexspi: new driver arm64: dts: ls1028a: fix FlexSPI clock arm64: dts: lx2160a: fix FlexSPI clock .../bindings/clock/fsl,flexspi-clock.yaml | 55 +++++++++ .../arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 15 ++- .../arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 15 ++- drivers/clk/Kconfig | 8 ++ drivers/clk/Makefile | 1 + drivers/clk/clk-divider.c | 34 ++++++ drivers/clk/clk-fsl-flexspi.c | 106 ++++++++++++++++++ include/linux/clk-provider.h | 27 +++++ 8 files changed, 257 insertions(+), 4 deletions(-) create mode 100644 Documentation/devicetree/bindings/clock/fsl,flexspi-clock.yaml create mode 100644 drivers/clk/clk-fsl-flexspi.c -- 2.20.1
